Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1998-08-20
2001-04-10
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S347000, C257S759000, C257S066000
Reexamination Certificate
active
06215130
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to thin film transistors (TFTs), and more particularly to TFT integrated circuits with new designs to facilitate interconnection.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits (ICs) are ubiquitous in commercial electronics. ICs for electronic logic and memory devices are nearly always silicon based devices and ICs for photonic applications are typically III-V and II-VI based devices. Transistors, both MOS and bipolar, are made by creating impurity regions in the semiconductor substrate, and forming polysilicon or metal electrodes on the surface of the semiconductor to contact or interact with the underlying semiconductor regions. Both planar and mesa substrate configurations are used. In the manufacture of these devices, the critical nature of the semiconductor substrate, and the formation of substrate layers and electrical contacts to the substrate, dictate that the fabrication sequence begins with processing the semiconductor substrate. Subsequently in the process, after the arrays of sources, drains and gates, or emitters, bases and collectors, are formed, contacts are made to these elements to form arrays of transistors. The final phase of the fabrication is to interconnect the arrays of transistors. Thus the typical semiconductor IC is built using many layers, beginning with an active semiconductor substrate. For example, in the manufacture of a typical silicon MOS transistor, the layers may comprise a field oxide, a gate dielectric, a gate metal layer, a first interlevel dielectric layer, a first level metal interconnection layer, a second interlevel dielectric layer, a second level metal layer, and an insulating capping layer. In the essential sequence of semiconductor IC manufacture to date, the metal interconnection layers are formed last. This sequence is advantageous as long as the critical fabrication steps are performed early in the process. This factor reduces device cost by having the highest incidence of processing failures occur early in the manufacturing sequence. However, a significant drawback to this sequence is that the elements formed by these early critical steps are vulnerable to processing conditions used in later steps to complete the device. This is especially true for the semiconductor substrate, the impurity regions in the substrate, and the interfaces between the semiconductor device elements and insulating and contact layers. These portions of the device are particularly sensitive to heat. Thus e.g. the techniques used to deposit metal interconnect layers and interlevel dielectrics have been developed with careful restrictions on thermal processing. Accordingly, the typical IC manufacturing process that has evolved over time is seriously constrained due to this well known thermal susceptibility.
As IC device density increases, interconnection issues become more prominent. While individual transistor design has dominated IC technology to date, device density is becoming so large that critical steps in future IC manufacturing are likely to involve metallization and interconnect operations. In that event the least costly processes will be those that can form the interconnections first. Moreover, even in relatively low cost IC technologies, where high transistor performance is not required, interconnection technology and robust interconnection strategies may become dominant design issues.
In recent years, IC technologies have been proposed that use organic semiconductor transistors. The chief attractions of such circuits stem from the anticipated ease of processing and compatibility with flexible substrates. These advantages are expected to translate into a low-cost IC technology suitable for applications such as smart cards, electronic tags, and displays.
TFT devices are described in F. Garnier et al., Science, Vol. 265, pp. 1684-1686; H. Koezuka et al., Applied Physics Letters, Vol. 62 (15), pp. 1794-1796; H. Fuchigami et al., Applied Physics Letters, Vol. 63 (10), pp. 1372-1374; G. Horowitz et al., J. Applied Physics, Vol. 70(1), pp. 469-475; and G. Horowitz et al., Synthetic Metals, Vol. 42-43, pp. 1127-1130. The devices described in these references are based on polymers or oligomers as the active materials, in contrast with the amorphous silicon TFT structures that were developed earlier. The devices are typically field effect transistors (FETs). Polymer active devices have significant advantages over semiconductor TFTs in terms of simplicity of processing and resultant low cost. They are also compatible with polymer substrates used widely for interconnect substrates. Polymer TFTs are potentially flexible, and polymer TFT ICs can be mounted directly on flexible printed circuit boards. They also have compatible coefficients of thermal expansion so that solder bonds, conductive expoxy bonds, and other interconnections experience less strain than with semiconductor IC/polymer interconnect substrate combinations. While MIS FET devices are most likely to find widespread commercial applications, TFT devices that utilize both p-type and n-type organic active materials are also known. See e.g., U.S. Pat. No. 5,315,129. S. Miyauchi et al., Synthetic Metals, 41-43 (1991), pp. 1155-1158, disclose a junction FET that comprises a layer of p-type polythiophene on n-type silicon.
Recent advances in polymer based TFT devices are described in U.S. Pat. No. 5,596,208, issued May 10, 1996, U.S. Pat. No. 5,625,199, issued Apr. 29, 1997, and U.S. Pat. No. 5,574,291, issued Nov. 12, 1996, all of which are incorporated herein by reference, especially for descriptions of useful materials. With the development of both n-type and p-type active polymer materials, as described in these patents, complementary ICs can be readily implemented, as detailed particularly in U.S. Pat. No. 5,625,199.
For the purpose of definition the term organic semiconductor is intended to define that category of materials which contain a substantial amount of carbon in combination with other elements, or that comprises an allotrope of elemental carbon, and exhibits charge carrier mobility of at least 10
−3
cm
2
/Vs at room temperature (20° C.). Organic semiconductors of interest for TFTs typically have conductivity less than about 1 S/cm at 20° C.
Although the new TFT devices represent a significant departure from the semiconductor IC technology of the past, the configurations of these devices, and the overall fabrication approach, follow closely those used for silicon IC fabrication. For example, even though the substrate in these TFT devices is as critical an element as in traditional IC structures, either from the standpoint of performance or manufacturing yield, these IC devices are consistently produced by forming the active devices in a transistor array, and then forming the interconnections.
SUMMARY OF THE INVENTION
We have developed a radically new approach to integrated circuit fabrication in which the interconnections are formed prior to forming the active transistors. The IC devices resulting from this sequence have inverted structures, with the interconnections buried next to the substrate and the active elements on top. This approach follows an analysis of transistor fabrication sequence, and the realization that the use of organic semiconductor active materials removes critical constraints present in traditional semiconductor IC manufacturing. In particular, the thermal constraints mentioned earlier are removed, allowing a wide choice of processing conditions for fabricating the interconnection levels. Moreover, if interconnection strategies, performance and yield become dominant with new low cost TFT technologies, this invention allows the interconnection phase of TFT IC manufacture to occur early in the sequence, thus affording the potential for higher yields and lower cost.
REFERENCES:
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5321286 (1994-06-01), Koyama et al.
patent: 5347144 (1994-09-01), Garnier et al.
patent: 5365081 (1994-11-01), Yamazaki et al.
patent: 5470776 (1995-11-01), Ryou
patent: 5
Loke Steven
Lucent Technologies - Inc.
Owens Douglas W.
Thomas Kayden Horstemeyer & Risley LLP
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