Thin film transistor with a sub-gate structure and a drain offse

Details Thin film transistor with a sub-gate structure and a drain offse Thin film transistor with a sub-gate structure and a drain offse

1993-11-08

1995-12-12

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 57, 257 61, 257365, 257366, H01L 2976, H01L 2904, H01L 31036, H01L 2994

Patent

active

054752388

ABSTRACT:
A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized. This may provide a reduction of a leakage current and a security of a high ON-current.

REFERENCES:
patent: 5124769 (1992-06-01), Tanaka et al.
patent: 5266507 (1993-11-01), Wu
IEEE Electron Device Letters, vol. 11, No. 11, Nov. 1990, "Device Sensitivity of Field-Plated Polysilicon High-Voltage TFT's and Their Application to Low Voltage Operation", by Huang et al. pp. 541-543.
"Field-Induction-Drain (FID) Poly-Si TFTs with High On/Off Current Ratio", Extended Abstracts of the 22nd (1990 International) Conference on Solid State Devices and Materials, Sendai, 1990, by Keiji Tanaka, et al., pp. 1011-1014.
"The Influence of Substrate Bias on Bottom Gate Type Poly Si TFTs", by K. Hamada et al., VLSI Development Division, NEC Corporation, one page, including English language statement of relevance.

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