Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1997-06-20
2001-04-17
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S380000, C257S393000, C257S904000
Reexamination Certificate
active
06218724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices having an internal voltage generation circuit and thin film transistors used therein and, more particularly, to a semiconductor memory device with reduced power consumption and a thin film transistor for achieving reduction in power consumption of a semiconductor memory device.
2. Description of the Background Art
A conventional internal voltage generation circuit which can be used in a Static Random Access Memory (hereinafter referred to as “SRAM”) is disclosed, for example, Japanese Patent Laying-Open No. 3-207091. The conventional internal voltage generation circuit will be described below.
FIG. 23
is a circuit diagram showing in detail a portion of an SRAM having the conventional internal voltage generation circuit.
Referring to
FIG. 23
, the SRAM with the conventional internal voltage generation circuit includes an internal circuit
1
and a voltage-down circuit
57
as an internal voltage generation circuit. Voltage-down circuit
57
includes resistors R
1
, R
2
and R
3
, PMOS transistors QP
1
and QP
2
, and an NMOS transistor QN.
Resistors R
1
and R
2
are connected in series between a node having an external power supply voltage Vcc and a node having a ground voltage. PMOS transistor QP
1
and resistor R
3
are connected in series between a node having external power supply voltage Vcc and a node having the ground voltage. The gate of PMOS transistor QP
1
and a node N
1
are connected.
PMOS transistor QP
2
is connected between a node with external power supply voltage Vcc and a node N
3
. PMOS transistor QP
2
has a gate connected to a node N
2
. NMOS transistor QN is connected between a node with external power supply voltage Vcc and node N
3
. NMOS transistor QN has a gate connected to a node with external power supply voltage Vcc. Node N
3
is connected to internal circuit
1
.
Here, internal circuit
1
is such circuit as a memory circuit. Description will now be made of operation of voltage-down circuit
57
.
When external power supply voltage Vcc is a low voltage of, for example, 3 V, PMOS transistor QP
1
is turned off by the voltage of node N
1
determined by the ratio of the resistance of resistor R
1
to that of resistor R
2
. Node N
2
has a voltage reduced to approximately 0 V by resistor R
3
. As a result, PMOS transistor QP
2
is turned on and node N
3
receives external power supply voltage Vcc of 3 V. Thus, external power supply voltage Vcc of 3 V is supplied to internal circuit
1
.
In contrast, when external power supply voltage Vcc is increased to a high voltage of, for example, 5 V exceeding a predetermined voltage, PMOS transistor QP
1
is turned on by the voltage of node N
1
. The voltage of node N
2
is increased to external power supply voltage Vcc, thereby turning off PMOS transistor QP
2
. As a result, the voltage (current) to be applied to internal circuit
1
is all conveyed through NMOS transistor QN. Thus, internal circuit
1
receives a voltage of approximately 3.5 V obtained by reducing external power supply voltage Vcc of 5 V by a threshold voltage Vtn of NMOS transistor QN.
Thus, when external power supply voltage Vcc exceeds a predetermined voltage, a voltage is applied by NMOS transistor QN, thereby preventing application of a high voltage to internal circuit
1
to secure reliability. In addition, when external power supply voltage Vcc is decreased to a voltage lower than a predetermined voltage, a voltage is applied mainly by PMOS transistor QP
2
to avoid loss of data in the memory circuit (memory cell) as internal circuit
1
.
As described above, conventional voltage-down circuit
57
is capable of retaining data at a lOW voltdge and reducing a high voltage. Here, the value of the predetermined voltage (hereinafter referred to as “switching point”) as a condition for turning off PMOS transistor QP
2
(turning on PMOS transistor QP
1
) is determined mainly by the ratio of the resistance of resistor R
1
to that of resistor R
2
.
More specifically, the condition for switching direct application of external power supply voltage Vcc to internal circuit
1
by PMOS transistor QP
2
and application of the external power supply voltage Vcc which is reduced by threshold voltage Vtn to internal circuit
1
by the diode-connected NMOS transistor QN is determined mainly by the ratio of the resistance of resistor R
1
to that of R
2
.
Resistors R
1
, R
2
and R
3
are resistance elements with high resistance which are formed of polysilicon.
As described above, conventional voltage-down circuit
57
employs one resistance element as resistor R
1
. The same applies to resistors R
2
and R
3
. Therefore, in a process of fabricating resistors R
1
and R
2
, the actual resistance value may be different from the designed resistance value due to displacement of the mask and other factors, whereby the above-described switching point cannot be determined as designed.
Furthermore, if resistance values of resistors R
1
-R
3
are increased for reduction in consumed current in conventional voltage-down circuit
57
, the response speed of voltage-down circuit
57
to external power supply voltage Vcc (the speed at which the voltage of node N
1
changes in response to a change in external power supply voltage Vcc) is decreased, thereby causing malfunction of voltage-down circuit
57
.
More specifically, PMOS transistor QP
2
may not be turned off (PMOS transistor QP
1
may not be turned on) even if external power supply voltage Vcc exceeds the above-described switching point (predetermined voltage), and PMOS transistor QP
2
may not be turned on (PMOS transistor QP
1
may not be turned off) even if external power supply voltage Vcc falls below the above-described switching point (predetermined voltage).
Especially, when external power supply voltage Vcc greatly changes during, for example, power-on, an abnormal ordinary voltage may be applied to internal circuit
1
because of slow response of voltage-down circuit
57
to external power supply voltage Vcc. More specifically, since voltage-down circuit
57
responds slowly to external power supply voltage Vcc, PMOS transistor QP
2
is not turned off (PMOS transistor QP
1
is not turned on) even when external power supply voltage Vcc exceeds the above-described switching point (predetermined voltage). As a result, external power supply voltage Vcc which is a high voltage exceeding the above-described switching point is undesirably applied to internal circuit
1
.
SUMMARY OF THE INVENTION
The present invention overcomes the problems as described above, and an object thereof is to provide a semiconductor memory device having an internal voltage generation circuit capable of preventing change in switching point even if the resistance value of a resistor determining the switching point deviates from the designed resistance value.
Another object of the present invention is to provide a semiconductor memory device having an internal voltage generation circuit capable of enhancing response speed to an external power supply voltage and preventing malfunction.
Still another object of the present invention is to provide a thin film transistor capable of achieving reduction in power consumption of the thin film transistor with high resistance and of a semiconductor memory device.
The semiconductor memory device according to one aspect of the present invention relates to a semiconductor memory device provided with an internal circuit including a plurality of memory cells for storing information, which device includes a first resistance portion connected between a first line for applying a first power supply voltage and a first node, a second resistance portion connected between the first node and a second line for applying a second power supply voltage, a first transistor of a first conductivity type connected between the first line and a second node and having a control electrode connected to the first node, a third resistance portion connected between the second node and the second line, a second
Hirose Toshihiko
Maegawa Shigeto
Ukita Motomu
Baumeister Bradley W.
Jackson, Jr. Jerome
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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