Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-12-18
2004-12-07
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S061000, C257S072000, C257S344000, C257S408000, C359S016000
Reexamination Certificate
active
06828585
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a thin-film transistor preferably for use in an active-matrix-addressed liquid crystal display device, contact image sensor and other suitable devices and also relates to a method for fabricating such a transistor.
Recently, an active-matrix-addressed liquid crystal display device has been used as a display device for personal computers, TV sets of a reduced thickness, camcorders and so on. In an active-matrix-addressed liquid crystal display device, a thin-film transistor (TFT) is extensively used as a switching element that selectively turns a pixel ON or OFF. A TFT is provided for each of a huge number of pixels so that each of those pixels has its ON/OFF states controlled by its associated TFT.
When a TFT turns ON responsive a scanning signal that has been applied to the gate of the TFT, a predetermined signal voltage is applied to a pixel electrode, which is connected to the drain of the TFT, by way of a data bus line connected to the source of the TFT. In a liquid crystal display device, the orientation state of its liquid crystal layer changes in accordance with the level of a signal voltage applied to a pixel electrode. And by utilizing this change in orientation, an image is displayed thereon.
In an interval after a predetermined signal voltage has been applied to a pixel electrode and before another signal voltage is newly applied to this pixel electrode (i.e., one frame interval), no scanning signal is applied to the gate of a TFT associated with the pixel electrode. That is to say, the TFT is kept OFF to maintain a predetermined display state by keeping the potential level at the pixel electrode constant during this interval. While the TFT is OFF, the amount of current flowing through the TFT (i.e., leakage current or OFF-state current) is preferably as small as possible. This is because if an excessive amount of OFF-state current flows through the TFT, then the liquid crystal layer cannot maintain its desired orientation state and the resultant display quality deteriorates.
Particularly in a TFT including a polysilicon layer as its semiconductor layer, a greater amount of OFF-state current tends to flow through the TFT as compared to a TFT including an amorphous silicon layer as its semiconductor. This is because field-effect mobility is higher in a polysilicon layer than in an amorphous silicon layer. Accordingly, it is even more difficult to maintain the potential level of a pixel electrode associated with such a TFT.
Also, the higher the definition of a display device, the greater the number of pixels the display device should include. If the number of pixels included in a display device is increased, then each of those pixels should be driven in a shorter period of time. In that case, a greater amount of ON-state current should flow through each TFT.
Furthermore, in a small-sized high-definition liquid crystal display for a liquid crystal projector, for example, the size of each pixel has been further reduced. To increase the brightness of an image presented on such a display, the aperture ratio needs to be increased for each pixel region and each TFT needs to be further downsized. On the other hand, to mass-produce an enormous number of display devices at a high yield, measures should be taken against TFT leakage failures resulting from various types of defects.
In summary, a TFT, particularly one for use to drive its associated pixel in a small-sized high-definition liquid crystal display, preferably has:
1) small leakage current;
2) large ON-state current;
3) small size; and
4) no leakage failures.
A TFT having these advantageous features is disclosed in Japanese Laid-Open Publication No. 7-263705, for example. The TFT has a so-called “multi-gate structure” and a so-called “LDD (lightly doped drain) structure” in combination. Hereinafter, the TFT disclosed in this publication will be described with reference to FIG.
11
.
In the TFT
90
shown in
FIG. 11
, a pair of gate electrodes
96
a
and
96
b
is formed over a semiconductor thin film
92
with an insulating film
94
interposed therebetween. Channel regions
97
a
and
97
b
are defined in parts of the semiconductor thin film
92
that are located under the gate electrodes
96
a
and
96
b
, respectively. And the channel regions
97
a
and
97
b
are interposed or surrounded by lightly doped regions
98
a
and
98
b
and heavily doped regions (i.e., source/drain regions)
99
a
and
99
b
. Also, another lightly doped region (intermediate region)
95
is defined between the channel regions
97
a
and
97
b.
By interposing the lightly-doped region (LDD region)
98
b
between the drain region (i.e., the heavily doped region)
99
b
and channel region
97
b
, the intensity of an electric field is weakened at the end of the drain region
99
b
, thus reducing the leakage current. Also, this TFT has a multi-gate structure having an equivalent circuit configuration in which two single-gate TFTs are connected in series together. Thus, even if a leakage failure has been caused in one of the two TFTs, the other TFT still serves as a switching element. In this manner, redundancy is ensured for leakage failures.
In addition, in the TFT
90
disclosed in the publication identified above, the length of the intermediate region
95
is smaller than the total length of the lightly doped regions
98
a
and
98
b
, thereby increasing the amount of ON-state current. Furthermore, the TFT
90
includes no heavily doped region between the gate electrodes
96
a
and
96
b
. Thus, the space between the gate electrodes
96
a
and
96
b
may be narrowed, and therefore the TFT
90
may be downsized.
Hereinafter, it will be described with reference to
FIGS. 12A through 12G
how to fabricate a TFT substrate (including the TFT
90
) for a liquid crystal display device.
First, in the process step shown in
FIG. 12A
, a semiconductor thin film
92
of polysilicon (poly-Si), for example, is deposited on an active region on an insulating substrate
91
. Then, a surface portion of the semiconductor thin film
92
is oxidized, for example, thereby forming an insulating film
94
thereon.
Next, in the process step shown in
FIG. 12B
, dopant ions (e.g., B
+
ions) may be implanted at a predetermined dose (of e.g., about 1×10
12
/cm
2
to about 8×10
12
/cm
2
) into the entire semiconductor thin film
92
if necessary. In this process step, the characteristic of a channel region for the TFT is determined and the threshold voltage of the TFT is controlled.
Thereafter, in the process step shown in
FIG. 12C
, gate electrodes
96
a
and
96
b
are formed over the semiconductor thin film
92
that has been covered with the insulating film
94
. Specifically, the gate electrodes
96
a
and
96
b
may be formed by depositing a low-resistivity poly-Si thin film doped with phosphorus on the insulating film
94
and then by patterning the poly-Si thin film into a desired shape. It should be noted that if necessary, a silicon nitride film or any other suitable undercoat film may be formed on the insulating film
94
as shown in
FIG. 12C
before the gate electrodes
96
a
and
96
b
are formed thereon.
Then, in the process step shown in
FIG. 12D
, dopant ions (e.g., P
+
ions) are implanted at a relatively low dose into selected parts of the semiconductor thin film
92
using the gate electrodes
96
a
and
96
b
as a mask. In this manner, lightly doped regions are defined in those parts of the semiconductor thin film
92
, which are not covered with the gate electrodes
96
a
and
96
b
, so as to be self-aligned with the gate electrodes
96
a
and
96
b.
Subsequently, in the process step shown in
FIG. 12E
, a resist pattern
93
is defined so as to cover the gate electrodes
96
a
and
96
b
entirely and the surface of the insulating film
94
partially. The resist pattern
93
should be formed in such a manner that the right- and left-hand-side edges thereof are spaced apart from the associated side faces of the gate electrodes
96
a
and
96
b
by a predetermi
Nelms David
Tran Mai-Huong
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