Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2000-01-19
2001-12-25
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S059000, C257S401000
Reexamination Certificate
active
06333520
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a thin film transistor, a manufacturing method a thin film transistor, and a circuit and a liquid crystal display device each incorporating the thin film transistor.
DESCRIPTION OF RELATED ART
A polycrystalline silicon thin film transistor which can be formed at low processing temperature, i.e., “low temperature processed polysilicon TFT”, attracts attention as an element which enables the formation of a high-definition liquid crystal display comprising a large glass substrate containing a driver.
FIG.
38
A and
FIG. 38B
, which is a sectional view taken along line B—B of
FIG. 38A
, show, as an example of conventional polysilicon TFT, a top gate type TFT in which a polysilicon thin film which forms source and drain regions is positioned on the lower side, and a gate electrode is positioned on the upper side. This polysilicon TFT is an example of an N-channel TFT.
As shown in
FIGS. 38A and 38B
, a buffer layer
2
comprising a silicon oxide film is formed on a glass substrate
1
, and a polysilicon thin film
3
is formed on the buffer layer
2
. Further, a gate insulation film
4
comprising a silicon oxide film is formed to cover the polysilicon thin film
3
, and a gate electrode
5
comprising a tantalum nitride film, an aluminum (Al) film or the like is formed. Further, a source region
6
and a drain region
7
into which an N-type impurity is introduced are formed in portions of the polysilicon thin film
3
except at a portion directly below the gate electrode. Also, a layer insulation film
8
comprising a silicon oxide film is formed, contact holes
9
are formed, and a source electrode
10
and a drain electrode
11
are formed.
In the field of general semiconductor devices, in order to achieve a high-speed device, low power consumption, and higher function, miniaturization of devices and utilization of a SOI (Silicon On Insulator) structure have recently attracted attention. In the SOI structure, for example, single crystal silicon layers are formed to hold a silicon oxide film therebetween on the surface of a silicon substrate. However, while the SOI structure has the above advantages it also is influenced by a substrate floating effect because the transistor formation region and the support substrate are electrically isolated. In this case, the problem caused by the substrate floating effect is, for example, deterioration in voltage resistance between the source and drain. This occurs because the holes generated in a high electric field region near the drain region accumulate in a portion below the channel to increase the potential of the channel portion, and thus a parasitic bipolar transistor comprising source, channel and drain regions which serve as an emitter, a base and a collector, respectively, is turned on.
On the other hand, when a polysilicon TFT constructed as shown in
FIGS. 38A and 38B
is used as a liquid crystal driving element, a signal voltage is applied between the source electrode
10
and the drain electrode
11
, and a scanning voltage is applied to the gate electrode
5
. However, in this case, the same deterioration in characteristics which occur in the SOI structure due to the substrate floating effect also occurs.
Also, significant deterioration in TFT has been apparent. Since the channel region of TFT is surrounded by an insulation film, a structure is formed in which heat hardly escapes. Therefore, deterioration occurs due to the heat of the TFT itself which is generated during operation. Such deterioration significantly occurs in a TFT having a large channel width.
A polycrystalline silicon TFT exhibits a large leakage current (off current) during an off time and large variations in the amount of current, as compared with a single crystal silicon transistor. This tendency is more significant in low-temperature processed TFTs than TFTs formed by a high temperature process.
For example, as the leakage current (off current) of the TFT of a pixel portion increases, the luminance of a display screen largely varies, and TFT design becomes difficult due to variations in the leakage current (off current).
The present invention solves the above problem.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a thin film transistor having a structure in which the leakage current (off current) of the TFT is decreased, and variations in the leakage current (off current) are suppressed, a method of manufacturing a TFT, and a circuit and a liquid crystal display device each incorporating the thin film transistor.
In order to achieve the object, a thin film transistor of the present invention comprises a channel region formed in a non-single crystal silicon thin film on a substrate, first and second regions of a first conduction type formed in the non-single crystal silicon thin film to be separated with the channel region therebetween, and a carrier injection region into which carriers of the conduction type opposite to the first conduction type are generated in a high electric field region near the first or second region flow.
In accordance with the present invention, since the carrier injection region, into which hot carriers generated in the electric field region are flowed, is provided, the amount of the hot carriers flowing into the first or second region is decreased, thereby significantly decreasing deterioration in characteristics, as compared with a conventional thin film transistor.
The thin film transistor of the present invention comprises a channel region formed in a non-single crystal silicon thin film on a substrate, first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated with the channel region therebetween, and at least one third region of the conduction type opposite to the first conduction type which is formed between the first and second region in the non-single crystal silicon thin film.
In the present invention, a plurality of third regions may be formed on the non-single crystal silicon thin film.
The third region may be formed between at least one of the first and second regions and the channel region in the non-single crystal silicon thin film.
The third region may be formed in at least a portion of the channel region.
The first conduction type may be the N type.
The non-single crystal silicon thin film may be a polycrystalline silicon thin film.
The polycrystalline silicon thin film having the channel region, first region and second region may be formed by a low temperature process.
The thin film transistor of the present invention comprises a channel region formed in a non-single crystal silicon thin film on a substrate, and first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated with the channel region therebetween, wherein the width of at least the channel region of the non-single crystal silicon thin film is larger than the minimum width of the first and second regions.
The width of the channel region is preferably 50 &mgr;m or more.
The width of the channel region is preferably 100 &mgr;m or more.
The thin film transistor of the present invention comprises a plurality of non-single crystal silicon thin films formed to cross a gate electrode on a substrate, a channel region formed in each of the non-single crystal silicon thin films, and first and second regions of a first conduction type formed in the non-single crystal silicon thin film separated by the channel region therebetween, wherein the first and second regions of the plurality of non-single crystal silicon thin films are respectively connected to common electrodes.
The channel width of each of the non-single crystal silicon thin films is preferably 10 &mgr;m or less.
The dimension between the outermost sides of the plurality of non-single crystal silicon thin films is preferably 50 &mgr;m or more.
The length of the channel region is preferably 4 &mgr;m.
The thin film transistor of the present invention comprises a semiconductor thin film island provided on a substrate, source
Ngo Ngan V.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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