Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2003-07-11
2004-11-09
Chowdhury, Tarifur R. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C438S030000
Reexamination Certificate
active
06816209
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a thin film transistor used for an active-matrix-type liquid-crystal display and a method for fabricating the thin film transistor, and a liquid-crystal display panel using the thin film transistor.
2. Prior Art
An active-matrix-type liquid-crystal display unit using a thin film transistor realizes displaying by arranging gate electrodes (Y-electrodes) and data electrodes (X-electrodes) like a matrix, injecting liquid crystal between a TFT array substrate configured by arranging thin film transistors (TFTs) at intersections of the matrix and a substrate facing and superimposed above the TFT array substrate, controlling a voltage to be applied to the liquid crystal by the thin film transistors, and using the electro-optical effect of the liquid crystal.
In this case, a normal-stagger-type (top-gate-type) structure and a reverse-stagger-type (bottom-gate-type) structure are known as structures of a thin film transistor.
FIG. 7
shows a typical structure of a normal-stagger-type (top-gate-type) thin film transistor. As shown in
FIG. 7
, the top-gate-type thin film transistor is configured by forming an opaque film
102
on an insulating substrate
101
such as a glass substrate and providing an insulating film
103
made of silicon oxide SiOx, silicon nitride SiNx or the like on the opaque film
102
. Moreover, a drain electrode
104
and a source electrode
105
which are respectively configured of an ITO (indium-tin oxide) film are provided on the insulting film
103
by keeping a channel interval, an amorphous-silicon film (a-Si-film)
106
for covering the electrodes
104
and
105
is provided, a gate insulating film
107
made of SiOx, SiNx or the like is provided on the film
106
, and a gate electrode
108
is provided on the film
107
, and thereby an island-shaped region referred to as a-Si island is formed.
As a process for fabricating the thin film transistor, there is the so-called 7PEP (PEP: Photo Engraving Process) structure. In case of the 7PEP structure, the drain electrode
104
and source electrode
105
respectively made of an ITO film are patterned and then, the a-Si film
106
is formed through the CVD (Chemical Vapor Deposition) art and patterned like an island. Thereafter, the gate insulating film
107
is formed through the CVD art and patterned into a predetermined shape. Thereafter, a TFT is completed by forming, for example, an aluminum (Al) film as the gate electrode
108
through sputtering and by patterning the film.
However, because the number of steps increases in case of the 7PEP structure, a next-generation 4PEP structure requiring a less number of steps is proposed. The 4PEP structure is configured by etching the gate insulating film
107
and a-Si film
106
below the gate electrode
108
at the same time. That is, the gate electrode
108
, gate insulating film
107
, and a-Si film
106
are continuously etched through one-time patterning process by using a gate-electrode plating pattern as a mask. Therefore, the 4PEP structure is very superior in reduction of the number of manufacturing steps.
Though not concerned with reduction of the number of manufacturing steps, there is the official gazette of Japanesse Published Unexamined Patent Application No. 1-68968 as a background art relating to an electrode structure of the present invention. This official gazette discloses a thin film transistor art of arranging a source electrode and a drain electrode in parallel with each other and moreover making these electrodes orthogonal to a gate electrode.
Moreover, a display data signal and a scanning signal are supplied to a drain line and a gate line connected with a thin film transistor from an external unit. In general, a gate line is connected to a gate electrode on an insulating film made of SiOx or SiNx provided on an insulating substrate. Therefore, portions corresponding to the gate insulating film
107
and a-Si film
106
below the gate electrode
108
in a thin film transistor structure are generally removed in case of a gate-line structure excluding an a-Si island.
However, when using the above 4PEP structure in order to reduce the number of steps, a structure similar to an a-Si island is also formed on a gate line because etching and forming a three-layer film through a patterning process once. That is, the a-Si film
106
and gate insulating film
107
unnecessary for the structure cannot be removed from a gate line exceeding an a-Si island and thereby, the films
106
and
107
are directly formed.
FIG. 8
is a top view of a thin film transistor under the above state. A TFT necessary as a liquid-crystal display panel is an a-Si island
111
formed on a gate electrode
108
serving as a protruded portion of a gate line
109
. However, another TFT is present on the gate line
109
other than the a-Si island
111
due to the above 4PEP structure. Therefore, a leak current shown by arrows in
FIG. 8
are generated from adjacent other data lines
110
, adjacent other drain electrodes
104
or the like, and flows into a source electrode
105
and thereby, an extra current flows through a display electrode
112
. As a result, no sufficient potential is written in a pixel due to an extra current (crosstalk) and this insufficient write causes extreme deterioration of a display image.
The present invention is made to solve the above technical problems and its object is to reduce the number of necessary steps in a thin-film-transistor manufacturing process and prevent an abnormal potential from occurring due to a leak current from other data lines.
It is another object of the present invention to provide a thin film transistor capable of preventing flickering or sticking due to the change of capacities Cgs between a gate and a source even if a pattern is shifted between a gate line and a signal line.
SUMMARY OF THE INVENTION
To solve the above problems, a thin film transistor of the present invention is mounted on a predetermined substrate and provided with a gate electrode formed into a predetermined pattern, a semiconductor layer formed correspondingly to the patterning of the gate electrode, a pixel electrode interposed by the semiconductor layer, and a signal electrode interposed by the semiconductor layer by keeping a predetermined interval from the pixel electrode. The signal electrode is formed at a position for preventing crosstalk running from an adjacent signal electrode to the pixel electrode through the semiconductor layer.
In this case, it is also possible to pattern-form a gate insulating film together with the semiconductor layer correspondingly to the patterning of the gate electrode. Specifically, it is preferable to constitute the semiconductor layer and the gate insulating film so that they are formed in accordance with almost the same pattern as the case of the patterning of the gate electrode.
Moreover, a structure of a thin film transistor of the present invention is allowed to use not only the normal-stagger type (top-gate-type) but also the reverse-stagger type (bottom-gate type). In case of the reverse-stagger type (bottom-gate type), a gate electrode-can-be provided on a substrate and a semiconductor layer can be formed above the gate electrode through a gate insulating film as well as pattern-formed correspondingly to the patterning of the gate electrode. On the other hand, in case of the normal-stagger type (top-gate type), a semiconductor layer can be formed on a layer lower than a gate insulating film formed on the lower layer of a gate electrode. Application to the normal-stagger type (top-gate type) is particularly superior because the number of photomask steps can be easily reduced.
Moreover, by disposing a signal electrode at a position for preventing crosstalk running from an adjacent signal electrode to a pixel electrode through a semiconductor layer, it is possible to prevent a leak current from other signal line which should not flow into the pixel electrode. More specifically, it is preferable to dispose a signal electrode so as
Miyamoto Takashi
Morooka Mitsuo
Tokuhiro Osamu
Tsujimura Takatoshi
Akkapeddi P. R.
Chowdhury Tarifur R.
International Business Machines - Corporation
Scully Scott Murphy & Presser
Trepp, Esq. Robert M.
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