Thin film transistor having increased effective channel width

Details Thin film transistor having increased effective channel width Thin film transistor having increased effective channel width

1995-08-28

1997-08-12

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257347, H01L 2904, H01L 31036, H01L 310376, H01L 3120

Patent

active

056568223

ABSTRACT:
The longitudinal edges of the overlying channel layer of a thin-film transistor are substantially aligned with the longitudinal edges of the underlying polysilicon gate layer. As a result of this line-on-line arrangement of the channel and gate layers, integration area is minimized so that optimum integration density is achieved. Source-to-drain on current is increased as the result of the increased channel width gained from the sidewall section of the polysilicon gate, which may occur as a result of the permissible lateral extension of the body (channel) layer over one longitudinal edge of the channel gate layer due to a misalignment in lithography or processing delta.

REFERENCES:
patent: 4720736 (1988-01-01), Takafugi et al.
patent: 5115289 (1992-05-01), Hisamoto et al.
patent: 5202572 (1993-04-01), Kobayashi
patent: 5283455 (1994-02-01), Inoue et al.

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