Thin-film transistor having an inlaid thin-film channel region

Details Thin-film transistor having an inlaid thin-film channel region Thin-film transistor having an inlaid thin-film channel region

1993-10-04

1995-06-20

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 67, 257351, 257900, 257903, 257411, H01L 2701, H01L 2712

Patent

active

054263158

ABSTRACT:
A thin-film transistor having a thin-film channel region (20) inlaid in a recess (29) along the wall of a multi-layered insulating structure (14), and a gate electrode (12) electrically controlling current conduction in the thin-film channel (20) and separated therefrom by a gate dielectric layer (32). The multi-layered insulating structure (14) includes a spacing layer (28) which is withdrawn from the wall of the multi-layered insulating structure (14) and forms an inner wall of the recess (29). By residing in the recess (29), the thin-film channel region (20) is aligned to the multi-layered insulating structure (14) and the gate dielectric layer (32) separates exposed portions of the thin-film channel region (20) from the gate electrode (12). Thin-film source and drain regions (16, 18) are integral with the thin-film channel region (20) and are self-aligned to the multi-layered insulating structure (14).

REFERENCES:
patent: 4966864 (1990-10-01), Pfiester
patent: 5083190 (1992-01-01), Pfiester
patent: 5233207 (1993-08-01), Anzai
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5309010 (1994-05-01), Kitajima

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