Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Patent
1996-11-01
1997-08-19
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
257345, 257607, H01L 29786
Patent
active
056591837
ABSTRACT:
A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type. A thin film transistor includes, ii) a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity of a second type to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of the second type to a second concentration, the second concentration being less than the first concentration; and ii) a gate positioned operatively adjacent the channel region. Alternately, the drain offset region consists essentially of undoped semiconductive material.
REFERENCES:
patent: 4318216 (1982-03-01), Hsu
patent: 5021845 (1991-06-01), Hashimoto
patent: 5104818 (1992-04-01), Silver
patent: 5124769 (1992-06-01), Tanaka et al.
patent: 5348897 (1994-09-01), Yen
patent: 5396099 (1995-03-01), Kitatima
patent: 5422505 (1995-06-01), Shirai
patent: 5434093 (1995-07-01), Chau et al.
patent: 5510278 (1996-04-01), Nguyen et al.
Furuta, Hiroshi et al., "Hot-Carrier Induced Ion/Ioff Improvement Of Offset PMOS TFT", NEC Corporation, 1991, pp. 27-28. no month.
Ohkubo, H. et al., "16 Mbit SRAM Cell Technologies for 2.0V Operation", IEDM, 1991, pp. 481-484. no month.
Wolf, S., "Silicon Processing For The VLSI Era--vol. 2: Process Integration", .RTM.1990 Lattice Press, pp. 66-69. no month.
Batra Shubneesh
Manning Monte
Hardy David B.
Micro)n Technology, Inc.
Thomas Tom
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