Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
1999-06-02
2003-09-30
Parker, Kenneth (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S043000
Reexamination Certificate
active
06628363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (hereinafter referred to as “TFT”) having an interlayer insulating film and to a display using the TFT as a switching element.
2. Description of the Prior Art
Recent development is directed toward TFTs which use a polycrystalline silicon film as an active layer and which are used as a driver element and/or a pixel driving element for an active matrix type liquid crystal display (hereinafter referred to as “LCD”) or an organic EL (Electro Luminescence) display.
A conventional TFT is described hereinbelow.
FIG. 1
is a block configuration diagram of a typical LCD.
As shown in the diagram, the LCD comprises a display part provided with TFTS for driving display pixels and a drive circuit for driving the TFTs of the display part, the drive circuit including a scanning side drive circuit
10
and a horizontal side drive circuit
20
.
The scanning side drive circuit
10
is provided with a vertical side shift register
11
and a buffer array
12
, while the horizontal side drive circuit
20
is provided with a horizontal side shift register
21
, a buffer array
22
and a source line switch array
23
.
FIG. 2
is a TFT top plane view of a buffer constituting the conventional horizontal side drive circuit
20
.
FIG. 3
is a sectional view taken along a line
2
A—
2
A of FIG.
2
.
Referring to
FIG. 3
, the structure of the TFT of the buffer is described.
On an insulating substrate
510
made of quartz glass or non-alkaline glass, there are formed in the mentioned order a gate electrode
511
made of a refractory metal (high melting point metal) such as chromium (Cr) or molybdenum (Mo), gate insulating film
512
and an active layer
513
made of a polycrystalline silicon film.
The active layer
513
is provided with channels
515
and
516
positioned over the gate electrode
511
and with sources
518
and
521
and drains
519
and
520
which are positioned on both sides of the channels
515
and
516
and which are formed by ion implantation with stoppers
517
serving as masks on the channels
515
and
516
. In
FIGS. 2 and 3
, the TFT on the right of the diagrams is an n-type channel TFT in which impurity ions of phosphorus (P) or the like are doped into the source
518
and the drain
519
, whereas the TFT on the left of the diagram is a p-type channel TFT in which impurity ions of boron (B) or the like are doped into the source
521
and the drain
520
.
Then, on top of all the surfaces of the gate insulating film
512
, active layer
513
and stopper
517
there are formed an interlayer insulating film
522
consisting of an SiO
2
film, an SiN film and an SiO
2
film which are placed in this order. Metal such as Al is then filled into contact holes provided correspondingly to the sources
518
and
521
and the drains
519
and
520
to thereby form source electrodes
27
and
25
and a drain electrode
24
. In this case, the drain electrode
24
connected to the drains
519
and
520
are shared by the n-type channel TFT and the p-type channel TFT. On top of all the surfaces there is further formed a planarization film
26
made of, e.g., organic resin for making the surfaces planar. An inverter
500
consisting of the n-type channel TFT and the p-type channel TFT is thus formed. Another inverter
400
also has the same structure.
Liquid crystal is then filled into the cell gap between the substrate provided with the horizontal side drive circuit including inverters
400
and
500
, the vertical side drive circuit and the display pixels, and the substrate confronting the above substrate, to thereby obtain an LCD.
In the conventional TFT, however, impurities from the sealing adhesive occurring upon the positioning to join the two substrates together or impurity ions occurring in the TFT manufacturing steps, may adhere to the top or bottom of the planarization insulating film of the TFT to be charged, with the result that a back channel may be formed in the TFT, causing a variation in the threshold voltage of the TFT. Disadvantageously, this resulted in an increase of the current consumption.
SUMMARY OF THE INVENTION
The present invention has been conceived in view of the conventional drawbacks described above. It is therefore the object of the present invention to provide a TFT having a stable threshold voltage as well as a display capable of suppressing an increase in the current consumption, by preventing impurities or other foreign matter from adhering to the top or bottom of the planarization insulating film of the TFT, or even in the case that electric charges are generated.
A TFT of the present invention comprises, on an insulating substrate, a gate electrode, a gate insulating film, a semiconductor film provided with an n-type channel and a source and a drain, an interlayer insulating film, a first electrode connected to the source of the semiconductor film, a second electrode to which a higher voltage than a voltage applied to the first electrode is applied and which is connected to the drain, and a planarization insulating film, said first electrode being disposed in such a manner as to overlap at least the n-type channel.
The above gate electrode is subjected mainly to a relatively low voltage.
A TFT of the present invention comprises, on an insulating substrate, a gate electrode, a gate insulating film, a semiconductor film provided with a p-type channel and a source and a drain, an interlayer insulating film, a first electrode connected to the drain of the semiconductor film, a second electrode subjected to a higher voltage than the voltage applied to the first electrode, the second electrode being connected to the source of the semiconductor film, and a planarization insulating film, wherein the second electrode is disposed in such a manner as to overlap at least the p-type channel.
Further, the above gate electrode is subjected mainly to a relatively high voltage.
A thin film transistor according to another aspect of the present invention comprises a gate electrode, a gate insulating film, a semiconductor film provided with a channel and a source and a drain, an interlayer insulating film, a source electrode connected to the source, and a drain electrode connected to the drain, wherein the source electrode is extended in such a manner as to overlap a channel formation position.
This thin film transistor may employ a configuration in which the channel is a n-type channel, with the gate electrode being subjected to a low level voltage acting as an off voltage for a long period of time.
This thin film transistor may also employ a configuration in which the channel is a p-type channel, with the gate electrode being subjected to a high level voltage acting as an off voltage for a long period of time.
The above thin film transistor can be a bottom gate type transistor having its gate electrode formed under the semiconductor film, with its source electrode covering the top of the channel with the interlayer insulating film therebetween. Alternatively, the above TFT can also be a top gate type transistor having its gate electrode formed over the semiconductor film, with its source electrode extending in such a manner as to cover the top area of the channel of the interlayer insulating film covering the gate electrode and semiconductor film.
In those configurations, according to a further aspect of the present invention, a planarization insulating layer is provided for covering the interlayer insulating film, the source electrode and the drain electrode to thereby flatten the surface.
The thin film transistor subjected to an off voltage for a long period of time is liable to suffer from a variation in characteristics of current and voltage. Thus, by configuring at least the thin film transistor driven in such a condition so that its channel overlaps the source electrode, it is possible to prevent an occurrence of a back channel as a result of accumulation of electric charge attributable to the impurity ions which may invade during the element forming process
Sano Keiichi
Segawa Yasuo
Tabuchi Norio
Yamada Tsutomu
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