Thin film transistor constructions with polycrystalline silicon-

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Non-single crystal – or recrystallized – material containing...

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257 19, 257 66, 257192, 257616, H01L 2904, H01L 2912, H01L 31036, H01L 2976

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059775602

ABSTRACT:
A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium. A method of increasing the size of individual crystal grains in a polycrystalline silicon alloy includes, a) providing germanium atoms within a layer of polycrystalline silicon to form a polycrystalline silicon-germanium alloy; and b) heating the polycrystalline silicon-germanium alloy to an effective temperature for an effective period of time to cause individual polycrystalline silicon grains within the alloy to increase their size from prior to the heating step.

REFERENCES:
patent: 4885614 (1989-12-01), Furukawa et al.
patent: 4891329 (1990-01-01), Reisman et al.
patent: 5166084 (1992-11-01), Pfiester
patent: 5218213 (1993-06-01), Gaul et al.
patent: 5240876 (1993-08-01), Gaul et al.
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5241197 (1993-08-01), Murakami et al.
patent: 5246886 (1993-09-01), Sakai et al.
patent: 5268324 (1993-12-01), Aitken et al.
patent: 5296386 (1994-03-01), Aronowitz et al.
patent: 5323020 (1994-06-01), Mohammad et al.
patent: 5323031 (1994-06-01), Shoji et al.
patent: 5324122 (1994-06-01), Roth et al.
patent: 5354700 (1994-10-01), Huang et al.
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5479033 (1995-12-01), Baca et al.
patent: 5527724 (1996-06-01), Brady et al.
patent: 5591653 (1997-01-01), Sameshima et al.
patent: 5665981 (1997-09-01), Banerjee et al.
Kuo, et al., "Modeling The Effect of Back Gate Bias On The Subthreshold Behavior Of A SiGe-Channel SOI PMOS Device," Solid-State Electronics, vol. 36, No. 12, pp. 1757-1761, Great Britain, Dec. 1993.
Eberl, K. "growth and strain compensation in the ternary Si(1-x-y)Ge(x)C(y) alloy system", Appl Phys. lett. vol. 60(24), pp. 3033-3035, Jun. 15, 1992.
Yonehara, et al., "Abnormal Grain Growth In Ultra-Thin Films of Germanium on Insulator", Mat. Res. Soc. Symp. Proc., vol. 25, pp. 517-524, 1984.
Lee, et al., "Characteristic Comparison Between Ge-On-Insulator (GOI) and Si-On-Insulator (SOI) Beam-Induced Crystallization Mechanism," Mat. Res. Soc. Symp. Proc., vol. 74, pp. 577-583, 1987.
Hinckley, et al., "Charged Carrier Transport in Si.sub.1-x Ge.sub.x Pseudomorphic Alloys Matched to Si-Strain Related Transport Improvements," Appl. Phys. Lett., vol. 55, pp. 2008-2010, Nov., 1989.
Kesan, et al., "High Performance 0.25 .mu.m p-MOSFETs With Silicon-Germanium Channels for 300K and 77K Operations," IDEM Tech. Dig., pp. 25-28, 1991.
Nayak, et. al., "Enhancement-Mode Quantum-Well Ge.sub.x Si.sub.1-x PMOS," IEEE Electron Device Letters, vol. 12, No. 4, pp. 154-156, Apr., 1991.
Nayak, et al., "High Performance GeSi Quantum-Well PMOS On SIMOX," IEDM Tech. Dig., pp. 777-780, 1992.
Nayak, et al., "High-Mobility GeSi PMOS On SIMOX," IEEE Electron Device Letters, vol. 14, No. 11, pp. 520-522, Nov. 1993.
Fukami, "Characterization of SiGe/Si Heterostructures Formed by Ge/sup =/ and C/sup =/ Implantation", Abstract, in Appl. Phys. Lett., Nov. 1990.
Yan, et al., "Amorphous Silicon, Germanium, and Silicon-Germanium Alloy Thin-Film Transistor Performance and Evaluation", Appl. Phys. Lett. vol. 50, No. 19, May 1987, pp. 1367-1369.

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