Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-04-09
2001-07-31
Lao, Lun-Yi (Department: 2672)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C330S257000, C330S288000
Reexamination Certificate
active
06268842
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit for a semiconductor display device using thin film transistors. Particularly, the invention relates to a differential amplifying circuit and a buffer using the same, which is used for a driver circuit of an active matrix type semiconductor display device. Moreover, the invention relates to a semiconductor display device using the driver circuit.
2. Description of the Related Art
In recent years, a technique for manufacturing a thin film transistor (TFT) using a semiconductor thin film formed on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for an active matrix type liquid crystal display device and an electroluminescence (EL) display device has been increased.
In the active matrix type liquid crystal display device, a TFT is disposed for each of several hundred thousands to millions of pixels arranged in matrix, and an electric charge going in and out of each pixel electrode is controlled by a switching function of the TFT.
FIG. 10
shows a structure of a conventional active matrix type liquid crystal display device. Shift registers and buffer circuits are generically called a driver circuit, and are integrally formed on the same substrate together with an active matrix circuit in recent years. Reference numeral
1001
denotes a source signal line side driver circuit, and
1002
denotes a gate signal line side driver circuit.
Reference numeral
1003
denotes an active matrix circuit, and pixel TFTs
1004
are disposed in matrix. A pixel electrode is connected to a drain electrode of each of the pixel TFTs
1004
. A liquid crystal material is put between the pixel electrode and its opposite electrode and is sealed. An auxiliary capacitor
1006
for holding an electric charge is provided for each of the pixel TFTs
1004
.
There is also known a structure in which quartz is used for a substrate and a thin film transistor is manufactured with a polycrystal silicon film.
There is also known a technique in which a thin film transistor using a crystalline silicon film is manufactured on a glass substrate by using a technique such as laser annealing. When this technique is used, it is possible to integrate an active matrix circuit and a driver circuit on the glass substrate.
In the structure shown in
FIG. 10
, a picture signal supplied to a picture signal line is selected by a timing signal from a shift register circuit of the source signal line side driver circuit. Then a designated picture signal is supplied to a corresponding source signal line. A timing signal from the gate signal line side driver circuit is supplied to a corresponding gate signal line (scanning line). The picture signal supplied to the source signal line is written in the pixel electrode of a thin film transistor of a pixel selected by the timing signal from the gate signal line.
By sequentially repeating the foregoing operation at suitable timing, information is sequentially written in the respective pixels arranged in matrix.
When picture information for one picture (one frame) is written, writing of picture information for a next picture is carried out. In this way, display of a picture is sequentially carried out. In general, writing of information for one picture is carried out 30 times or 60 times per second.
Here, an example of the source signal line side driver circuit will be shown in FIG.
11
. Reference numeral
1100
denotes a clock input terminal,
1101
denotes a clock line,
1102
denotes a start pulse input terminal,
1103
to
1105
denote shift registers,
1106
to
1111
denote inverter-type buffers,
1112
denotes a video signal input terminal,
1113
denotes a video signal line,
1114
to
1116
and
1120
to
1122
denote switches,
1117
to
1119
and
1125
to
1127
denote holding capacitors,
1123
denotes a transfer signal input terminal,
1124
denotes a transfer signal line,
1128
to
1130
denote analog buffers, and
1131
to
1133
denote source signal line connection terminals.
In the case of analog gradation, a video signal which is continuous in time series is used as a gradation signal inputted to the source signal line side driver circuit. In the case of a normally white mode (display mode in which white display is effected when a voltage is not applied to a liquid crystal), it is set such that as an absolute value of a voltage of a gradation signal becomes large, the display approaches black display. With respect to the shift registers
1103
to
1105
, a start pulse synchronous with a video signal is inputted to the start pulse input terminal
1102
, and is sequentially shifted by a clock pulse inputted from the clock pulse line. The output of the shift registers
1103
to
1105
is inputted into a sampling circuit through the inverter-type buffers
1106
to
1111
.
The sampling circuit is constituted of the switches
1114
to
1116
and the holding capacitors
1117
to
1119
. The switches
1114
to
1116
are sometimes called transmission gates. Turning On or OFF of the switches
1114
to
1116
is controlled by the buffer circuits. In the ON state, the video signal line is short-circuited to the holding capacitors
1117
to
1119
, and electric charges are stored in the holding capacitors
1117
to
1119
. When a start pulse is inputted and the pulse passes through the shift registers, the output of the buffer circuits is inverted, and the switches
1114
to
1116
are turned OFF.
When the switches
1114
to
1116
are turned OFF, the electric charges stored in the holding capacitors
1117
to
1119
are held, and the electric potential is held until the next time the switches
1114
to
1116
are turned ON. In a period between a time point when sampling of video data for one line is ended and a time point when sampling for the next line is started, a transfer signal is inputted from the transfer signal input terminal
1123
, and this transfer signal is supplied from the transfer signal line. The switches
1120
to
1122
are turned ON by this transfer signal, electric charges are stored in the holding capacitors
1125
to
1127
, and the electric potentials of the holding capacitors
1117
to
1119
are transferred to the holding capacitors
1125
to
1127
. When the switches
1120
to
1122
are turned OFF, the electric potentials of the holding capacitors
1125
to
1127
are held.
The holding capacitors
1125
to
1127
are connected with the analog buffers
1128
to
1130
, and the source signal lines
1131
to
1133
are driven through the analog buffers
1128
to
1130
. These analog buffers
1128
to
1130
are circuits necessary for driving the source signal lines without affecting the electric potentials of the holding capacitors.
Here, an example of a conventional circuit used for the analog buffers
1128
to
1130
will be shown in FIG.
12
. Reference numeral
1201
denotes a terminal to which a holding capacitor is connected, and which is an input end of a signal. Reference numeral
1202
denotes a terminal to which a source signal line is connected, and which is an output end of a signal. Reference numeral
1203
denotes a constant current source,
1204
denotes a constant voltage source,
1205
and
1206
denote P-channel TFTs, and
1207
and
1208
denote N-channel TFTs. In the analog buffer of
FIG. 12
, a differential circuit A is constituted of the P-channel TFTs, and a current mirror circuit B is constituted of the N-channel TFTs.
The operation of the analog buffer of
FIG. 12
will be described. In the case where the electric potential of the input end
1201
of the differential circuit connected to the holding capacitor is increased, an input current of the current mirror circuit
1210
connected to a reversed-phase output of the input end
1201
is decreased, and the output current of the current mirror circuit
1210
is decreased in proportion to that. On the other hand, a current of the same phase at the input end is increased, so that the electric potential at the output end
1202
is increased and r
Koyama Jun
Yamazaki Shunpei
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Lao Lun-Yi
Semiconductor Energy Laboratory Co,. Ltd.
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