Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2000-10-12
2003-01-28
Faberry, Wael (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S059000, C257S072000, C349S138000, C349S140000
Reexamination Certificate
active
06512243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT) assembly, and in particular, to a TFT suitable for a liquid crystal display (LCD) device, and a method of fabricating the same.
2. Description of the Related Art
Generally, a TFT is used as a switching element in, for example, art LCD device. A well known TFT assembly includes a substrate, gate and data lines formed on the substrate in a matrix pattern, and gate and data pads for transmitting drive signals from a drive circuit to the gate and data lines.
FIG. 1
schematically illustrates gate and data pads of a TFT assembly, and
FIG. 2
shows an enlarged view of a circled portion A of
FIG. 1
for illustrating a portion where gate pads and link lines are formed.
Referring first to
FIG. 1
, a TFT assembly comprises a plurality of gate pads
10
connected to gate lines (not shown) formed an a substrate
40
, and a plurality of data pads
20
connected to data lines (not shown) formed on the substrate
40
. The gate and data lines are generally arranged to form a matrix pattern (not shown). As shown in
FIG. 2
, gate drive signals are transmitted from a drive circuit (not shown) to the gate pads
10
, and from the gate pads to the gate lines through link lines
11
. The gate drive signals transmitted to the gate lines are further transmitted to corresponding thin film transistors to drive the same. Short circuits frequently occur during the manufacturing of the TFT assembly between adjacent pads
10
and between adjacent link lines
11
due to metal remainders or residues
14
a
and
14
b
, respectively.
The metal remainders
14
a
and lab will be described in more detail with reference to
FIGS. 3
a
and
3
b
, which are sectional views taken along lines I—I and II—II of
FIG. 2
, respectively.
Referring first to
FIG. 3
a
, there is provided a substrate
13
on which the gate pads
10
are deposited using, for example, an aluminum evaporation process. Formed on the gate pads
10
is a metal layer
16
made of, for example, molybdenum (Mo) to prevent hillock from occurring on the aluminum surfaces of gate pads
10
. Deposited on the substrate
13
to cover the gate pads
10
and the metal layer
16
are, in order, a gate insulating layer
17
and a passivation layer
18
that are made of a silicon oxide or a silicon nitride. In addition, contact holes are formed by etching portions of the gate insulating and passivation layers
17
and
18
, which correspond to the gate pads
10
, using, for example, a masking process, such that the metal layer
16
is exposed. Indium tin oxide (ITO) electrodes
19
are formed on the passivation layer
18
such that they contact the metal layer
16
through the contact holes.
Referring to
FIG. 3
b
, a structure of the link line portion is substantially the same as that of the pad portion shown is
FIG. 3
a
except that there are no contact holes is the gate insulating and passivation layers
17
and
18
. That is, portions of the gate insulating and passivation layer
17
and
18
corresponding to the link lines
11
are not etched. The ITO electrodes
19
are formed an the portions of the passivation layer
18
corresponding to the link lines
11
.
In the above described TFT assembly, during an aluminum evaporation process for forming the pads
10
and the link lines
11
, or during a masking process for forming the metal layer
16
, metal remainders
14
a
or
14
b
may be formed on the substrate. The metal remainders
14
a
or
14
b
may electrically interconnect the adjacent pads
10
or the adjacent link lines
11
, as shown in
FIGS. 3
a
and
3
b
. The metal remainders
14
a
and
14
b
cause a short circuit between the adjacent pads
10
and between the adjacent link lines
11
.
In an effort to overcome this drawback, a short circuit inspecting device has been used to detect short circuits in the TFT assembly and to repair the same. For example, metal remainders (short circuits) may be disconnected using a laser after being detected. However, this process is time consuming and reduces overall manufacturing productivity.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a TFT assembly and a method of fabricating the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
It is an object of the present invention to provide a TFT assembly having a structure for preventing a short circuit from occurring between adjacent pads or between adjacent links.
It is another object of the present invention to provide a method of fabricating a TFT assembly including a step for preventing a short circuit from occurring between adjacent pads or between adjacent links.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance wish the purpose of the present invention, as embodied and broadly described, the present invention provides a method of fabricating a semiconductor device having a plurality of conductive structures formed on a substrate for transmitting signals, the method comprising the steps of forming a plurality of conductive structures on the substrate; depositing an insulating layer on the conductive structures and the substrate; and etching portions of the insulating layer between adjacent conductive structures to expose a surface of the substrate, thereby preventing an electrical shore between the adjacent conductive structures.
According to another embodiment of the present invention, a method of fabricating a semiconductor device comprises the steps of forming a plurality of pads on the substrate depositing an insulating layer on the substrate; and forming an electrode pattern on the insulating layer, the electrode pattern contacting the pads through a plurality of contact holes formed in the insulating layer, wherein the insulating layer between adjacent pads is etched to expose a surface of the substrate, whereby a short between the adjacent pads due to a metal remainder formed when the pads are formed is prevented.
According to another aspect of the present invention, a semiconductor device comprises a substrate; a plurality of conductive structures on the substrate; an insulating layer on the substrate and the conductive structures; an electrode pattern on the insulating layer, the electrode pattern contacting at least some of the conductive structures through a plurality of contact hales in the insulating layer; and at least one insulating channel between adjacent conductive structures, a surface of the substrate being exposed through the insulating channel.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 6153893 (2000-11-01), Inoue et al.
Kim Joo-Young
Kim Woong-Kwon
Oh Young-Jin
Faberry Wael
Kebede Brook
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
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