Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2000-12-06
2002-09-10
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000
Reexamination Certificate
active
06448579
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 1999-21033, filed on Jun. 7, 1999, under 35 U.S.C. § 119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Liquid Crystal Display (LCD), and more particularly, to a Thin Film Transistor (TFT) array substrate and to a method of fabricating the same.
2. Description of Related Art
Generally, a liquid crystal display (LCD) comprises opposed upper and lower substrates and an interposed liquid crystal. On the lower substrate, a plurality of gate lines extending in one direction and a plurality of data lines extending in a perpendicular direction are formed. Within this matrix arrangement is a plurality of thin film transistors (TFTs) disposed near the crossings of the data and gate lines. The TFTs are used as switches that selectively apply voltages across the liquid crystal.
Nowadays, the liquid crystal display (LCD) is frequently used in computers, such as laptop computers. While liquid crystal displays started out as relatively simple display devices, they have become large and relatively complex displays. A large-sized LCD employs an active matrix array substrate that includes numerous pixel regions, data and gate lines that cross each other to define the pixel regions, and TFTs (switching device) positioned near the crossings of the data and gate lines.
With such active matrix type liquid crystal displays, high picture quality and high definition are important. To help achieve such features, storage capacitors in parallel with pixel electrodes have been used.
In general, without a storage capacitor, the electric charge of a first signal applied through the TFT will leak away after a short time. In contrast, with a storage capacitor the first electric charge is maintained until the application of a second signal.
In general, for the storage capacitor the gate line acts as one capacitor electrode and the pixel electrode acts as the other capacitor electrode.
FIG. 1
is an enlarged plan view illustrating the array substrate of a conventional active matrix type LCD having a pixel region “P”, a storage capacitor “C”, a TFT “A” and gate and data lines
36
and
49
. A drain electrode
47
of the TFT “A” is connected to a pixel electrode
40
of the pixel region “P” via a contact hole
57
.
A semiconductor channel region
53
is formed between source and drain electrodes
45
and
47
by exposing a portion of the intrinsic semiconductor layer
39
. Ohmic contact regions are formed between the intrinsic semiconductor layer
39
and the source and drain electrodes
45
and
47
. Gate and data pads (not shown) are formed at one end of the gate and data lines
36
and
49
.
FIGS. 2
a
to
2
f
are cross-sectional views taken along line I-I of
FIG. 1
, and are used to illustrate process steps of fabricating a TFT array substrate using a conventional four-mask process.
Referring to
FIG. 2
a
, a first metallic layer is formed on a substrate
31
and is then patterned using a first mask process to form a gate pad (not shown), a gate electrode
33
and a gate line
36
. The first metallic layer is beneficially made of a metallic material having a low resistance, such as Aluminum (Al) or Al-alloy. When the gate line
36
is used as a capacitor electrode, the time constant of the gate line increases. Thus, a material having the low resistance, such as Aluminum, is preferably used for the gate line. Aluminum can decrease the time constant compared with a material having a higher resistance, such as Tantalum (Ta) or Chrome (Cr).
The gate electrode
33
is extended from the gate line
36
and is formed at the comer of the pixel region. Referring back to
FIG. 1
, a portion of the gate line
36
is used as a capacitor electrode of the storage capacitor “C”.
As shown in
FIG. 2
b
, a first insulation layer
37
is formed by depositing an inorganic substance, such as Silicon Nitride (SiN
x
) or Silicon Oxide (SiO
2
), or an organic substance, such as BCB (Benzocyclobutene) or acryl, on the substrate
31
while covering the gate electrode
33
and the gate line
36
(and thus the capacitor electrode). Then, an intrinsic semiconductor layer
39
, such as pure amorphous silicon, is formed on the first insulation layer
37
. Then, an extrinsic semiconductor layer
41
, such as impurity (n+ or p+) doped amorphous silicon, is sequentially formed on the intrinsic semiconductor layer
39
. Then, a second metallic layer
43
made of a material such as Molybdenum (Mo), Tantalum (Ta), Tungsten (W), Antimony (Sb) or the like is formed on the extrinsic semiconductor layer
41
.
Referring to
FIG. 2
c
, the source and drain electrodes
45
and
47
, data line
49
(see FIG.
1
), data pad (not shown) and second capacitor electrode
51
having an island shape are formed by patterning the second metallic layer
43
and the extrinsic semiconductor layer
41
using a second mask process. The source and drain electrodes
45
and
47
are spaced apart from each other to expose the semiconductor channel region
53
. At this time, the extrinsic semiconductor layer
41
is removed using the source and drain electrodes
45
and
47
as a mask. Moreover, careful is required in this step, so as not to pattern the intrinsic semiconductor layer
39
.
The portions of the extrinsic semiconductor layer
41
between the intrinsic semiconductor layer
39
and the source and drain electrodes
45
and
47
act as ohmic contact layers
43
a
and
43
b
, respectively.
As shown in
FIG. 2
d
, a second insulation layer or protection layer
53
is formed on the metallic layers
45
,
47
and
51
, and on the intrinsic semiconductor layer
39
.
Referring to
FIG. 2
e
, contact holes
55
and
57
are formed by patterning the protection layer
53
. Simultaneously, the pixel region “P” is formed by patterning the protection layer
53
, the intrinsic semiconductor layer
39
, and the first insulation layer
37
using a third mask process, except for the region for the storage capacitor and the data line.
Referring to
FIG. 2
f
, a transparent conductive substance such as ITO (indium-tin-oxide) is deposited and patterned using a fourth mask process to form a pixel electrode
40
. Thus, the pixel electrode
40
, which electrically connects to the second capacitor electrode
51
and to the drain electrode
47
via contact holes
55
and
57
, is formed.
FIG. 3
a
is an enlarged view illustrating the portion “C” of
FIG. 2
f
, while
FIG. 3
b
is an equivalent circuit of
FIG. 3
a.
As shown in
FIGS. 3
a
and
3
b
, the storage capacitor “C” includes the first capacitor electrode/gate line
36
. It also includes the second capacitor electrode
51
(having a contact with the pixel electrode
40
), the first insulation layer
37
(which stores the electric charge as a dielectric layer), and the semiconductor layer
42
(the intrinsic and extrinsic semiconductor layers
39
and
41
that act as a dielectric layer).
According to the conventional method for manufacturing a TFT array substrate using a four-mask process, the process steps are reduced over a five-mask process. However, the storage capacitance is also decreased compared to the five-mask process. For a better understanding, the storage capacitance is represented by the following equation:
C
st
=
ϵ
·
A
d
(
1
)
In the above equation (1), “C
st
” denotes capacity, “∈” denotes a dielectric constant of the dielectric layer, “d” represents the thickness of the dielectric layer and “A” represents the area of the capacitor electrode. As described by Equation (1), the storage capacitance “C
st
” is in proportion to the area “A” and is in inverse proportion to the thickness “d” of the dielectric layer.
Therefore, due to the fact that the dielectric layer includes two layers (the first insulation layer
37
and the semiconductor layer
42
) between the two capacitor electrodes
36
and
51
, in the conventional four-mask process the capacitance is less than it could be.
SUMMARY OF THE INVENTION
In
Kim Yong-Wan
Lim Byoung-Ho
L.G.Philips LCD Co., Ltd.
McKenna Long & Aldridge
Thomas Tom
Tran Thien F
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