Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-10-21
2004-11-16
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S066000, C349S046000
Reexamination Certificate
active
06818923
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2002-0021054, filed on Apr. 17, 2002, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to thin film transistor array substrates of the type used in liquid crystal displays. More particularly, this invention relates to a thin film transistor array substrate, and to its manufacturing method, that is fabricated using a reduced number of masks.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance using an electric field to produce an image. To this end, an LCD includes a liquid crystal panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal cells.
The liquid crystal display panel includes a thin film transistor array substrate and an opposed color filter array substrate. Spacers between two substrates main a constant cell gap, which is filled by a liquid crystal.
The thin film transistor array substrate has gate lines and data lines, thin film transistor switching devices at intersections of the gate lines and the data lines, pixel electrodes in liquid crystal cells defined by the crossing gate and data lines, with the pixel electrodes being connected to the thin film transistors, and alignment films. The gate lines and the data lines receive signals from driving circuits via pad portions. The thin film transistors apply pixel voltages on the data lines to the pixel electrodes in response to scanning signals applied to the gate lines.
The color filter array substrate consists of color filters for the liquid crystal cells, a black matrix that divides the color filters, a common electrode for applying a reference voltage to the liquid crystal cells, and an alignment film.
The liquid crystal display panel is made by preparing the thin film array substrate and the color filter array substrate individually, joining them, injecting a liquid crystal between those substrates, and then sealing the liquid crystal in place.
Since fabricating a thin film transistor array substrate requires multiple masking processes, manufacturing a thin film transistor array substrate is a major factor in the costs of a liquid crystal display panel. To reduce costs, significant effort has gone into reducing the required number of masking processes. This is because each mask process includes many sub-processes, such as deposition, cleaning, photolithography, etching, photoresist stripping and inspection. While the standard thin film transistor array substrate manufacturing process used five masks, a newer four-mask process has been developed.
FIG. 1
is a plan view illustrating a thin film transistor array substrate made by the four-mask process, and
FIG. 2
is a sectional view of the thin film transistor array substrate of
FIG. 1
taken along line A-A′. The thin film transistor array substrate includes crossing gate lines
2
and data lines
4
on a lower substrate
42
. A gate insulating film
44
separates the gate and data lines
2
and
4
. A thin film transistor
6
is provided at each intersection, and pixel electrodes
18
are provided in liquid crystal cells defined by the gate and data lines
2
and
4
. The thin film transistor array substrate includes storage capacitors
20
formed by overlaps of pixel electrodes
18
and gate lines
2
. Additionally, gate pad portions
26
connect to the gate lines
2
, and data pad portions
34
connects to the data lines
4
.
Each thin film transistor
6
includes a gate electrode
8
that is connected to a gate line
2
, a source electrode
10
that is connected to a data line
4
, a drain electrode
12
that is connected to a pixel electrode
18
, and an active layer
14
that overlap the gate electrode
8
and that defines a channel between the source electrode
10
and the drain electrode
12
. The thin film transistor
6
allows a pixel voltage signal applied to the data line
4
to be applied to the pixel electrode and sustained on a storage capacitor in response to a gate signal applied to the gate line
2
. The active layer
14
also overlaps the data pad
36
, the storage electrode
22
, and the data line
4
. On the active layer
14
is an ohmic contact layer
48
for making an ohmic contact.
As shown in FIG.
1
and
FIG. 2
, the pixel electrode
18
is connected, via a first contact hole
16
through a protective film
50
, to the drain electrode
12
. The pixel electrode
18
is used for producing a potential difference with respect to a common electrode on the upper substrate (not shown) when charged with a pixel voltage. This potential difference rotates the liquid crystal between the thin film transistor array substrate and the upper substrate owing to dielectric anisotropy. Thus, the pixel voltage controls the amount of light emitted by the upper substrate from a light source input through the pixel electrode
18
.
The storage capacitor
20
includes part of a “pre-stage” gate line
2
. The storage capacitor
20
also includes a storage electrode
22
that overlaps the gate line
2
, an interposed gate insulating film
44
, an interposed active layer
14
, and an interposed ohmic contact layer
48
. A pixel electrode
22
on the protective film
50
contacts the storage electrode
22
through a second contact hole
24
. The storage capacitor
20
maintains the pixel voltage on the pixel electrode
18
until the next pixel voltage is applied.
The gate line
2
is connected, via the gate pad portion
26
, to a gate driver (not shown). The gate pad portion
26
includes a gate pad
28
, which extends from the gate line
2
, and a gate pad protection electrode
32
that is connected, via a third contact hole
30
through the gate insulating film
44
and through the protective film
50
, to the gate pad
28
.
The data line
4
is connected, via the data pad portion
34
, to a data driver (not shown). The data pad portion
34
includes a data pad
36
that extends from the data line
4
, and a data pad protection electrode
40
that is connected, via a fourth contact hole
38
through the protective film
50
, to the data pad
36
.
Hereinafter, a method of fabricating the thin film transistor substrate of FIG.
1
and
FIG. 2
will be described with reference to
FIG. 3A
to FIG.
3
D. Referring to
FIG. 3A
, gate patterns are provided on the lower substrate
42
. To do so, a gate metal layer is formed on the upper substrate
42
by deposition, possibly sputtering. Then, the gate metal layer is patterned by photolithography and etching using a first mask process to form the gate line
2
, the gate electrode
8
, and the gate pad
28
. The gate metal layer can be a single-layer or double-layer structure of chrome (Cr), molybdenum (Mo), or aluminum.
Referring to
FIG. 3B
, the gate insulating film
44
, the active layer
14
, the ohmic contact layer
48
, and source/drain patterns are sequentially formed on the structure shown in FIG.
3
A. To do so, the gate insulating film
44
, an undoped amorphous silicon layer, an n
+
amorphous silicon layer, and source/drain metal layer are sequentially provided by deposition, beneficially plasma enhanced chemical vapor deposition (PECVD) or sputtering. Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at the channel region of the thin film transistor is used as a second mask. This allows the photo-resist pattern at channel regions to have a lower height than the remainder of the photoresist. Subsequently, the source/drain metal layer is patterned using a wet etching process to provide source/drain patterns that include the data line
4
, the source electrode
10
, the drain electrode
12
(which at this time is integral with the source electrode
10
), and the storage electrode
22
.
Next, the n
+
amorphous silicon layer and the amorphous silicon layer are patterned using a dry etching process and using the same p
Cho Heung Lyul
Kim Woong Kwon
Nam Seung Hee
Jackson Jerome
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
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