Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2000-08-03
2003-12-02
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S347000
Reexamination Certificate
active
06657226
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to a thin-film transistor array and, more particularly, to a thin-film transistor array that can be used with advantage for an active matrix liquid crystal display panel.
DISCUSSION ON THE RELATED ART
The following specific analyses have been given on the related art by the inventors in the course of the investigation toward the present invention.
An active matrix type liquid crystal display device, employing a thin-film transistor (‘TFT’) as a switching device, is made up of a TFT substrate comprised of a matrix array of TFTs and pixel electrodes and an opposing substrate electrode, arranged opposing the TFT substrate with a liquid crystal material interposed in-between. The opposing substrate electrode includes a light-shielding film (so-called black matrix), a color filter and a common electrode.
FIG. 15
shows a plan view illustrating the structure for one pixel of a typical thin-film transistor array, and
FIG. 16
shows a cross-sectional view taken along line G-G′ of FIG.
15
. This structure is referred to as ‘a first conventional technique’.
Referring to
FIGS. 15 and 16
, the structure of the first conventional technique is explained.
The active matrix type liquid crystal display device, employing the TFT as an active device, has a structure in which a gate bus line
111
, wired in the horizontal direction from a gate driver, and a drain bus line
112
, wired in the vertical direction from a source driver, are connected to a gate electrode
101
and a drain electrode
103
of the TFT device, respectively, and in which a pixel electrode
106
is connected to a source electrode
104
of the TFT device.
When a given gate line
111
goes high, the TFTs connected to this gate bus line
111
are turned on in unison. The pixel electrode
106
, connected to this TFT, is charged to a signal voltage applied to the drain bus line
112
.
If then the gate bus line
111
goes low, the TFT in the on-state is turned off. However, the pixel electrode
106
keeps on to maintain its charging voltage. This maintained voltage is rewritten by the next signal voltage when the corresponding TFT again goes on.
If the active matrix type liquid crystal display device employing this TFT substrate is to make display of satisfactory quality, it is necessary for the pixel electrode
106
to hold the charging voltage sufficiently until next rewriting.
FIG. 17
shows a cross-sectional view illustrating, step-by-step, the process for manufacturing a typical thin-film transistor array (first conventional technique) shown in FIG.
16
. Referring to
FIG. 17
, the manufacturing method according to the first conventional technique is explained.
A gate electrode
101
formed by a metal film of Cr or Al is patterned on a glass substrate
100
, as shown in
FIG. 17
a
. A gate insulating film
114
, a channel layer
102
of intrinsic semiconductor amorphous silicon ‘a-Si(n+)’ and a contact layer
107
of n+ semiconductor amorphous silicon (‘a-Si (n+)’ are formed sequentially thereon.
The semiconductor layer is then etched (
FIG. 17
b
) and the gate insulating film
114
of the contact area interconnecting the gate layer and the drain layer are removed by patterning, so that a through-hole, not shown, is formed for interconnecting a metal film forming the gate electrode
101
and a metal film forming the drain electrode
103
, source electrode
104
and the drain bus line
112
.
Similarly to the drain electrode
101
, the drain electrode
103
, source electrode
104
, drain bus line
112
and the pixel electrode
106
are formed (see
FIGS. 17
c
and
17
d
) and subsequently a passivation film
115
is formed to complete a TFT array substrate (see
FIG. 17
e
).
Meanwhile, a storage capacitance electrode
108
is formed simultaneously with the gate electrode
101
in the course of the patterning step for forming the gate electrode
101
. The storage capacitance electrode
108
faces the pixel electrode
106
via the gate insulating film
114
operating as a storage capacitance insulating film in-between to constitute a storage capacitance.
The opposing substrate side is manufactured by forming a counter-electrode on a glass substrate, not shown.
Finally, orientation films, not shown, are formed on the TFT array substrates and the opposing substrate, by way of orientation processing, after which a sealing pattern is formed and the substrates are then stacked together and fired. Into the fired product is injected a liquid crystal, not shown, and the injection inlet is sealed to complete a liquid crystal panel.
To this liquid crystal panel are added a light polarization plate, a driving circuit and a casing to complete a liquid crystal display device.
FIG. 18
shows a plan view illustrating the structure of one pixel of a representative thin-film transistor array characterized in that the storage capacitance is formed between it and the gate electrode (this structure is referred to as a ‘second conventional technique). The number of patterning steps and the manufacturing method in this structure are the same as those of the first conventional technique explained in accordance with FIG.
17
.
In the TFT of the structure shown in the first conventional technique and in the second conventional technique, the drain bus line
112
and the pixel electrode
106
are both electrically conductive layers each extending over the gate insulating film
114
, and are spaced apart from each other by a pre-set distance. However, if residual patterning troubles would occur in any patterning process, shorting is likely to occur between the drain bus line
112
and the pixel electrode
106
.
If shorting occurs between the drain bus line
112
and the pixel electrode, charging/discharging of the pixel electrode
106
cannot be controlled by on/off control of the TFT such that the pixels become visible as bright-point defect.
For reducing this shorting, there has been proposed in, for example, JP Patent Kokai JP-A-7-325314 a liquid crystal device in which, as shown in
FIG. 19
a
, by a step difference of the storage capacitance electrode
108
, the pixel electrode
106
in the vicinity of the storage capacitance electrode
108
is constricted or retracted, as shown in
FIG. 19
b
, relative to residual a-Si
116
, so that the drain bus line
112
and the pixel electrode
106
become difficult to get conductive by the residual a-Si
116
. The structure, however, cannot be applied to other than the case of residual a-Si attributable to the step difference of the storage capacitance electrode
108
.
There has also been proposed a TFT structure in which the drain bus line
112
and the pixel electrode
106
are laminated via an insulating film interposed in-between for reducing occurrences of shorting.
FIG. 20
shows, in a plan view, the structure for one pixel of a TFT array aimed at reducing the shorting between the drain bus line
112
and the pixel electrode
106
.
FIG. 21
is a cross-sectional view taken along line H-H′ in
FIG. 20
(third conventional technique).
Referring to
FIGS. 20 and 21
, the structure of the third conventional technique is explained.
In this third conventional technique, the drain bus line
112
is provided on the gate insulating film
114
, whilst the pixel electrode
106
is formed on a passivation film
115
. The drain bus line
112
and the pixel electrode
106
are separated on the layer basis by the passivation film
115
.
FIG. 22
is a process diagram showing, step-by-step, the manufacturing process for a thin-film transistor array (third conventional technique) aimed at reducing shorting between the drain bus line
112
and the pixel electrode
106
as shown in FIG.
21
. Referring to
FIG. 22
, the manufacturing method for this third conventional technique is explained.
On the glass substrate
100
was patterned a gate electrode
101
of a metal film, such as Cr or Al (see FIG.
22
a), after which the gate insulating film
114
and the channel layer
102
formed of a-Si(I) and a contact layer
107
formed of a-Si(n&p
Ohi Susumu
Taguchi Naoyuki
Abraham Fetsum
NEC LCD Technologies Ltd.
Sughrue & Mion, PLLC
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