Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1999-04-02
2001-09-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S067000, C257S068000, C257S069000, C257S070000, C257S071000, C257S072000
Reexamination Certificate
active
06288413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a thin film transistor and a method for producing the same. More specifically, the invention relates to a thin film transistor using a polycrystalline silicon produced at a low temperature.
2. Related Background Art
In recent years, active matrix type liquid,crystal displays (which will be hereinafter referred to as liquid crystal displays) are used for personal computers, word processors and portable information terminals, since liquid display systems are thin and light, able to be driven at a low voltage and easily applied to color display systems.
Among these displays, liquid crystal displays using thin film transistors (which will be hereinafter referred to as TFTs) as switching elements for pixel parts have been actively studied and developed, since such liquid crystal displays have a high display quality and a low electric power consumption.
TFTs are generally classified, in view of materials of active layers, into amorphous silicon TFTs using an amorphous silicon as the material of an active layer, and polycrystalline silicon TFTs using a polycrystalline silicon as the material of an active layer.
There is an advantage in that polycrystalline silicon TFTs have mobility about 10 to 100 times as high as that of amorphous silicon TFTs. Therefore, polycrystalline silicon TFTs are most suitable for pixel switching elements. In recent years, polycrystalline silicon TFTs are also used as elements of peripheral driving circuits. As a result, so-called pixel part-driving circuit integrated liquid crystal displays, wherein TFTs for pixel parts and TFTs for peripheral driving circuits are simultaneously formed on the same substrate, are actively studied and developed.
However, since polycrystalline silicon TFTs have a higher process temperature (e.g., 800° C., such polycrystalline silicon TFTs will be hereinafter referred to as high-temperature polycrystalline silicon TFT) than that of amorphous silicon TFTs, it is required to use an expensive, heat resisting glass substrate as an insulating substrate.
For that reason, low-temperature polycrystalline silicon TFTs having a low process temperature (e.g., 300° C.~600° C.) are widely noticed so that cheaper glass substrates can be used.
However, there is a problem in that low-temperature polycrystalline silicon TFTs have a higher value of resistance of a source-drain region of a contact layer than that of high-temperature polycrystalline silicon TFTs. Because the carrier concentration being in proportion to conductivity is low since the impurity activation rate for the source-drain region in a low temperature process is lower than that in a high temperature process. If the value of resistance of the source-drain region of the contact layer is high, the series resistor component increases, so that it is not possible to sufficiently obtain the ON current of TFTs, thereby deteriorating the picture quality.
In addition, since polycrystalline silicon TFTs have higher mobility than that of amorphous silicon TFTs, the scale down of TFTs can be achieved, whereas it is required to relieve the field intensity of a high field region generated in the vicinity of the drain of the active layer. If the field intensity in the vicinity of the drain is high, there are problems in that the impact ionization phenomenon and the carrier injection into the gate insulator film are caused to shift the gate threshold voltage (Vth) of the TFTs to deteriorate the reliability of the TFTS. There is particularly no problem if polycrystalline silicon TFTs are used for peripheral driving circuits, whereas there is a problem in that the picture quality deteriorates if polycrystalline silicon TFTs are used for pixel switching elements.
Therefore, in order to eliminate the aforementioned disadvantages, it is considered that polycrystalline silicon TFTs for pixel parts use a lightly doped drain (which will be hereinafter referred to as “LDD” or “n
−
”) structure, and n
+
-contact structure wherein a high concentration impurity is added to reduce the resistance of a source-drain contact layer.
FIGS. 7A through 7E
are sectional views showing a process for producing an array substrate for a liquid crystal display, which uses conventional high-temperature polycrystalline silicon TFTs as switching elements for pixel parts, the high-temperature polycrystalline silicon TFTs being produced by the thermal annealing at a temperature of higher than or equal to 800° C. to have a LDD structure and an n
+
-contact layer. In this liquid crystal display, the pixel parts and the peripheral driving circuit parts are formed on the same substrate. These drawings show only a CMOS transistor as the element of the peripheral driving circuit. The conductive type of the polycrystalline silicon TFTs used as the switching elements for the pixel parts is an n-type channel.
First, as shown in
FIG. 7A
, after a polycrystalline silicon film is formed on a transparent insulating substrate
81
, the polycrystalline silicon film is patterned to form active layers
82
a
through
82
c
. Then, after a gate insulator film
83
is formed on the whole surface, gate electrodes
84
a
through
84
c
are formed on the gate insulator film
83
.
Then, as shown in
FIG. 7B
, while a CMOS region for a peripheral driving circuit is covered with a resist
85
, phosphorus (P) is ion-implanted into a TFT region for a pixel part. As a result, an n
−
type source-drain region (which will be hereinafter referred to as a low-concentration n
−
type source-drain region)
86
, which has a relatively low impurity concentration (e.g., less than 1×10
18
cm
−3
), is formed so as to be self-aligned to the gate electrode
84
c.
Then, as shown in
FIG. 7C
, after the resist
85
is removed, P is ion-implanted while the p-type TFT region of the CMOS region for the peripheral driving circuit, the gate electrode
84
c
for the pixel part and the low-concentration n-type source-drain region
86
in the vicinity thereof are covered with a resist
87
. As a result, n
+
-type source-drain regions (which will be hereinafter referred to as high-concentration n
+
-type source-drain regions)
88
a
and
88
c
, which have a high impurity concentration (e.g., 1×10
20
cm
−3
), are formed. In order to reduce the resistance of the contact layer
88
c
, the impurity concentration of the regions
88
a
and
88
c
in a low temperature process must be higher than that in a high temperature process.
Then, as shown in
FIG. 7D
, after the resist
87
is removed, boron (B) is ion-implanted into the p-type TFT region of the CMOS region for the driving circuit part while the n-type TFT region of the CMOS region for the peripheral driving circuit and the TFT region for the pixel part are covered with a resist
89
. As a result, a p
+
-type source-drain region
88
b
having a relatively high impurity concentration (e.g., 10
19
~10
20
cm
−3
) is formed.
Finally, as shown in
FIG. 7E
, after the resist
89
is removed, the thermal activation of impurity (e.g., a high temperature thermal annealing at a temperature of higher than or equal to 800° C.), the preparation of an interlayer insulator film
90
and the preparation of a source-drain electrode
91
are subsequently carried out to accomplish the basic structures of each of TFTs. Thereafter, pixel electrodes (not shown) and so forth are formed to accomplish the basic structure of the array substrate.
However, in such a TFT having the LDD structure and the n
+
-contact structure, there are the following problems. That is, the low-concentration n
−
-type source-drain region
86
and the high-concentration n
+
type source-drain regions
88
a
and
88
c
have a low impurity activation rate, so that the junction to the n
−
region or the n-type channel is bad. Therefore, there is a problem in that a leak current (which will be hereinafter referred to as an OFF current for a TFT), which flows through the TFT when it is t
Ishizuka Yoshiki
Kamiura Norihiko
Fenty Jesse A
Kabushiki Kaisha Toshiba
Lee Eddie
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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