Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-01-05
2002-11-12
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S064000, C257S070000
Reexamination Certificate
active
06479837
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a thin-film transistor (TFT) using polycrystalline silicon thin-film as an active layer serving as a source area or a drain area, and a liquid crystal display unit (LCD) using such TFT.
BACKGROUND ART
There is at present a demand for a liquid crystal display unit capable of displaying at a higher speed, and as one of the means for satisfying such a requirement, it has been tried to change an active layer such as a gate area, a source area, or a drain area of the switching thin-film transistor that controls the liquid crystal layer from the amorphous silicon thin film into the polycrystalline silicon. This is the result obtained by paying attention to the fact that the mobility of the carrier in polycrystalline silicone is higher than that in amorphous silicon in principle.
In addition to formation of a polycrystalline silicon thin film having a high carrier mobility on an insulating substrate, it has been tried, not to externally attach a semiconductor chip having a single-crystal silicon active layer to the driving circuit of the liquid crystal display section as in the conventional art, but to simultaneously form a thin-film transistor having an active layer comprising a polycrystalline silicon thin film in the frame of the pixel section on the same substrate from the beginning.
We will now briefly describe with by referring to the drawings the process of forming a thin-film transistor by polycrystallizing this amorphous silicon, after forming an amorphous silicon thin film on a transparent insulating substrate such as a glass substrate, and the manufacturing method of a liquid crystal display unit using a thin-film transistor having an active layer comprising this polycrystalline silicon thin film, since they are related with the intent of the present invention although they may fall under the known conventional art.
FIG. 1
illustrates the state of changes in the cross section of a conventional thin film transistor using a polycrystalline silicon thin film as an active layer according to the progress of manufacture. Actually, a large number of the thin-film semiconductor for the pixels and the driving circuits thereof are formed and arranged in many rows and stages, i.e. the upper, lower, right, and left on the substrate in accordance with the layout of the liquid crystal display section. However, since this is a well known fact, and moreover, it is troublesome to show this process in detail, only one thin-film semiconductor is shown in this FIG.
1
.
In this
FIG. 1
,
1
represents an insulated substrate having transparency such as a glass,
2
represents a buffer layer for preventing an alkali metal or the like contained in the insulated substrate
1
from diffusing into an active layer comprising a silicon thin film and exerting an adverse Effect,
3
represents an amorphous silicon thin film; and
4
represents a polycrystalline silicon thin film.
5
represents a gate insulating film (layer) comprising, for example, SiO
2
and Si
3
N
4
and
6
represents a gate electrode.
7
represents a channel area and
8
represents a source area.
9
represents a drain area, and
10
represents a contact hole.
11
represents a source electrode, and
12
represents drain electrode.
A manufacturing method of a thin-film transistor using a polycrystalline silicon thin film as an active layer of thin-film transistor will now be described sequentially by referring to FIG.
1
.
(a) The amorphous silicon thin film
3
shall be formed by deposition on the insulated substrate via the buffer layer
2
;
(b) Polycrystallizing treatment of silicon shall be performed by applying a heat treatment to the amorphous silicon thin film
3
to. More particularly describing, the polycrystalline silicon thin film is obtained by irradiating an excimer laser (beam) onto the amorphous silicon thin film
3
, instantaneously melting the amorphous silicon, causing crystallization in accordance with cooling, and finally applying so-called laser annealing (or laser anneal technique). Then, unnecessary portions of the polycrystalline silicon thin film
4
on the substrate shall be removed, and the gate insulating film
5
and the gate electrode
6
shall sequentially be formed on the substrate.
In this state, impurities determining a type of conduction of the polycrystalline silicon thin film
4
such as phosphorus (P) or boron (B) are introduced from the upper section of the substrate into the polycrystalline silicon thin film
4
to form the source area and the drain area of the thin-film transistor, by using the gate electrode
6
as a mask, or simultaneously using a resist together if necessary, so as to prevent impurities from entering the channel area
7
. This introduction is usually accomplished by injecting P or B ions accelerated with a high voltage. A case with P ions are illustrated in FIG.
1
.
(c) The source area
8
and the drain area
9
are formed by activating the impurities through a heat treatment carried out by irradiating an excimer laser onto the polycrystalline silicon thin film
4
again.
(d) The source electrode
11
and the drain electrode
12
are formed by forming the contact hole
10
, and by burying a metal inside it.
Next, the thin-film transistor shown in
FIG. 1
is of so-called top-gate type in which a gate insulating layer is arranged on the substrate side of the gate electrode. As the applicable thin-film transistors for a liquid crystal unit include, apart from the top gate type, there is a type known as the bottom-gate type in which the gate insulating layer is arranged on the opposite side of the substrate against the gate electrode.
The bottom-gate type is advantageous in that it is capable to almost perfectely prevent impurities from diffusing from the undercoat such as the glass substrate to the channel area by means of the gate metal electrode. In this structure, however, because impurities forming the source area and the drain area cannot be diffused from the relatively thick substrate side, diffusion will be made from the silicon layer side after forming the silicon layer. As the result, it becomes difficult, or even impossible to perform self-alignment for forming the channel area, thereby causing deterioration of the transistor characteristics, such as a increased gate capacity.
On the other hand, a favorable feature of the top-gate type is that impurities forming the source area and the drain area is injected, from the gate electrode side after forming the silicon layer, by using the gate electrode as a mask, and thereby self-alignment will be permitted for forming the channel area. In this structure, however, since there is no gate metal under the channel area, diffusion of the impurities from the undercoat such as a glass substrate into the channel area during the subsequent heat treatment cannot completely be prevented, or is at least difficult to completely prevent such diffusion. If the thickness of the undercoat insulating film layer on the substrate is increased to avoid this defect, various problems such as cambering of the substrate will occur.
A conventional bottom -ate type thin-film transistor and a manufacturing method of it will now be described in detail by referring to the drawings.
FIG. 2
illustrates formation of the cross-section according to the progress of the manufacturing process of the conventional bottom-gate type thin-film transistor. In this
FIG. 2
, the numeral (latter we omit “the numeral”)
1
represents a transparent insulated substrate Comprising a glass or the like.
5
b
represents a gate insulating layer comprising SiO
2
or the like, and
6
b
represents a gate electrode.
7
b
represents a channel area in the silicon semiconductor layer, and
8
b
represents a source area in the silicon semiconductor layer.
9
b
represents a drain area in the silicon semiconductor layer, and
30
represents photo-resist.
5
c
represents an interlayer insulating layer,
11
b
represents a source electrode, and
12
b
represents a drain electrode.
The manufacturing method thereof will be de
Adachi Kazuyasu
Ogawa Kazufumi
Huynh Andy
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel L.L.P.
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