Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2001-12-12
2003-09-16
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S349000, C257S611000, C257S612000, C257S617000
Reexamination Certificate
active
06621101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a thin-film transistor (TFT), and more specifically, relates to an improved art of TFT transistor characteristics.
2. Description of Related Art
The various devices which use TFTs can include active matrix liquid display devices. For instance, FIG.
11
(A) shows an active matrix liquid crystal display device that is formed on a transparent substrate, such as glass, and having a roughly central region that is identified as a picture display region
81
. In this picture display region
81
, picture elements are formed into sections by data lines
90
and scanning lines
91
composed of a metal film, such as aluminum, tantalum, molybdenum, titanium and tungsten, a silicide film, a conductive semiconductor film, or the like. In each picture element, a liquid crystal unit
94
(liquid crystal cell) is formed where picture signals are input through a TFT
30
for picture switching. To the data lines
90
, a data-side drive circuit
60
is constructed that includes a shift register
84
, a level shifter
85
, video lines
87
and analog switches
86
. To the scanning lines
91
, scanning-side drive circuits
70
are constructed that have a shift register
88
and a level shifter
89
. In each picture element, a holding capacitor
40
is formed between the scanning line
91
and a capacity line
92
extending parallel thereto. The holding capacitor
40
has a function to improve the holding characteristics of charge at the liquid crystal units
94
. This holding capacitor
40
is sometimes formed between the scanning line
91
of the front stage and a picture element electrode.
At the data-side and the scanning-side drive circuits
60
and
70
, respectively, a CMOS circuit is constructed with an N type TFT
10
and a P type TFT
20
as shown in FIG.
11
(B). Such CMOS arrangement is used to implement an inverter circuit, etc. with more than one or two stages at the drive circuits
60
and
70
.
Therefore, on the active matrix substrate
200
, three types of TFTs are formed on the surface of the substrate that include an N type TFT
10
for the drive circuit, a P type TFT
20
for the drive circuit and an N type TFT
30
for picture element switching. However, these TFTs
10
,
20
and
30
have a common structure. Thus, in order to avoid redundancy of explanation, the structure of the N type TFT
10
for the drive circuit, as well as the manufacturing method thereof, will be explained with reference to
FIG. 12
,
FIG. 13
, FIG.
14
and FIG.
15
.
As illustrated in
FIG. 12
, on the active matrix substrate
200
, a bedding protective film
51
made of a silicon oxide film is formed at the surface side of the substrate
50
. On the surface of this bedding protective film
51
, a polycrystal semiconductor film
100
is formed that is patterned into island forms. On the surface of the semiconductor film
100
, a gate insulating film
12
is formed, and a gate electrode
14
is formed on the surface of this gate insulating film
12
. In the semiconductor film
100
, a channel region
15
is formed at a region facing the gate electrode
14
through the gate insulating film
12
. At the sides of this channel region
15
, a high concentration source region
16
and a high concentration drain region
17
are formed in a self-aligned condition relative to the gate electrode
14
. To the high concentration source region
16
and high concentration drain region
17
, a source electrode
41
and a drain electrode
42
are electrically connected respectively through contact holes in an interlayer insulating film
52
.
In order to manufacture the TFT
10
with such a structure, first, a substrate made of glass, etc. is cleaned by ultrasonic cleaning or the like as in
FIG. 13
(A). Subsequently, as shown in
FIG. 13
(B), a bedding protective film
51
is formed over the entire surface of the substrate
50
under the conditions of a substrate temperature from about 150 to 450° C.
Thereafter, as illustrated in
FIG. 13
(C), a semiconductor film
100
is formed on the surface of the bedding protective film
51
. At this time, by applying a low temperature process, the substrate
50
made of glass is prevented from being thermally deformed. A low temperature process indicates that the maximum temperature in the process (the maximum temperature wherein the temperature of a substrate as a whole increases at the same time) is lower than about 600° C. (preferably, less than about 500° C.). On the contrary, a high temperature process indicates that the maximum temperature of the process (the maximum temperature wherein the temperature of a substrate increases as a whole at the same time) is higher than about 600° C. This involves carrying out a high temperature procedure at 700-1,200° C. such as film-formation under high temperature and thermal oxidation of silicon.
However, since it is impossible to form a polycrystal semiconductor film directly on the substrate in the low temperature process as explained later, this semiconductor film
100
should be crystallized after an amorphous semiconductor film
100
is formed first by a plasma CVD method or a low pressure CVD method. Methods such as the Solid Phase Crystallization (SPC) method and Rapid Thermal Annealing (RTA) method for instance, are included as this crystallization method. As shown in
FIG. 13
(D), by carrying out laser annealing wherein excimer laser beams using XeCl are irradiated (ELA: Excimer Laser Annealing/crystallization process), the rise in substrate temperature is restrained, and polycrystal Si with a large grain diameter is also provided.
In this crystallization process, laser beams (excimer laser) from a laser beam source
320
, for example, are irradiated toward the substrate
50
that is placed on a stage
310
through an optical system
325
as shown in FIG.
14
. In this process, line beams L
0
wherein an irradiation range L is long in an X direction (for example, line beams at 200 Hz of laser pulse cyclic frequencies) are irradiated onto the semiconductor film
100
, and the irradiation region L is shifted in a Y direction. The beam lengths of the line beams L
0
are 400 mm herein, and the output intensity thereof is, for instance, 300 mJ/cm
2
. Also, in shifting the irradiation region L of laser beams in the Y direction, the line beams are scanned so as to overlap sections with 90% of the peak laser intensity in the width direction per region. As a result, the amorphous semiconductor film
100
is melted once, and is then polycrystallized after a cooling and solidifying process. In this process, the irradiation period of laser beams to each region is extremely short and the irradiation region L is local relative to the substrate as a whole, so that the substrate
50
as a whole is not heated to a high temperature at the same time. Thus, even though the glass substrate used as the substrate
50
is inferior to a quartz substrate in heat resistance, deformation, cracks, etc. are not formed by heat.
Next, as shown in
FIG. 13
(E), the polycrystal semiconductor film
100
is patterned in island forms by the photolithography technique.
Next, as illustrated in
FIG. 15
(A), a gate insulating film
12
made of a silicon oxide film is formed at the surface side of the semiconductor film
100
.
Next, as shown in
FIG. 15
(B), a conductive film
140
containing aluminum, tantalum, molybdenum, titanium, tungsten, etc. is formed by a sputtering method. After forming a resist mask
301
on the surface of the conductive film
140
, as shown in
FIG. 15
(C), the conductive film
140
is patterned and a gate electrode
14
is then formed as shown in
FIG. 15
(D).
Next, as illustrated in
FIG. 15
(E), phosphorus ions are introduced at the dosage of about e.g., 1×10
15
cm
−2
to the semiconductor film
100
with the gate electrode
14
as a mask. As a result, a source region
16
and a drain region
17
are formed in the semiconductor film
100
in a self-aligned condition relative to the gate electrode
14
and at the high concentration o
Migliorato Piero
Miyasaka Mitsutoshi
Yudasaka Ichio
Jackson Jerome
Oliff & Berridg,e PLC
Seiko Epson Corporation
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