Thin film SOI MOSFET

Details Thin film SOI MOSFET Thin film SOI MOSFET

1999-06-24

2002-06-25

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

Reexamination Certificate

active

06410973

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device, and more particularly, to the structure of a semiconductor device formed into a thin film semiconductor and a manufacturing process thereof.
BACKGROUND ART
A semiconductor integrated circuit having less floating capacity, obtains higher performance by isolating circuit elements with dielectric zones. In the case of forming transistors in a thin film silicon layer formed on an insulating film (hereinafter referred to as SOI layer), a so-called MESA isolation method is conventionally employed. In the MESA isolation method, the SOI layer between circuit elements are removed by etching to isolate the circuits elements, and transistors are formed in each completely island-like semiconductor layer. The MESA isolation method has many advantages, including freedom from latch-up with adjacent transistors.
FIGS. 30
to
44
are schematic views of a conventional SOI MOSFET. Specifically,
FIG. 30
is a plan view showing a structure of conventional SOI MOSFET.
FIGS. 31
to
44
are schematic views showing a manufacturing process of the transistor, and in which.
FIGS. 31
to
37
are sectional views taken along the line
31
-
37
of
FIG. 30
, and show the steps of the manufacturing process.
FIGS. 38
to
44
are sectional views taken along the line
38
-
40
of
FIG. 30
, and show the steps of the manufacturing process.
FIG. 37
shows a sectional structure taken along the line
31
-
37
of a plan structure of
FIG. 30
, and
FIG. 44
shows a sectional structure taken along the line
38
-
40
of FIG.
30
.
The SOI MOSFET is isolated by the MESA isolation method, and as illustrated in the drawings, a silicon-buried oxide film
2
is formed on a silicon substrate
1
to serve as an insulating substrate. A thin film silicon semiconductor layer
3
is further formed thereon, and divided into element forming regions
4
. A silicon oxide film
5
is filled-in or buried up to the same level as the element forming regions
4
so as to surround each region
4
.
A FET is formed in each of the element forming regions
4
, and the FET has a gate oxide film
7
, a polysilicon layer
8
serving as a gate electrode, an insulating film
9
on the sides of the gate electrode, and a source/drain region
10
. The gate electrode
8
is made of a polysilicon containing a phosphorus of not less than 1×10
20
/cm
3
in concentration. The insulating film
9
surrounds the gate insulating film
7
and the gate
8
. The semiconductor device further comprises an interlayer oxide film
11
and metal leads
12
.
A manufacturing process of the SOI MOSFET is hereinafter described with reference to
FIGS. 31
to
44
. First, as illustrated in
FIGS. 31 and 38
, the surface of the SOI substrate
14
comprising the silicon substrate
1
, buried oxide film
2
and SOI. layer
3
are subject to oxidation up to 100 to 200 Å in film thickness, forming oxide film
15
. Then, a resist
18
is formed, and part of the SOI layer
3
and overlapping oxide film
15
are removed by dry etching, whereby the element forming regions (active regions)
4
are formed. The isolation method called MESA isolation thus cuts electrical connection between adjacent transistors by removing part of the SOI. Then, channel doping is performed to establish a threshold voltage respectively for the NMOS FET and the PMOS FET, though not illustrated. A resist is formed only on the PMOS region, and boron ions of 1 to 6×10
12
/cm
2
are implanted at 20 KeV into the NMOS region. This is the channel doping for the NMOSFET. Further, after removing the resist of the PMOS region, a resist is formed again only on the NMOS region, and phosphorus ions of 1 to 3×10
11
/cm
2
are implanted at 30 KeV into the PMOS region. This is the channel doping for the PMOSFET.
Then, as illustrated in
FIGS. 32 and 39
, an oxide film
21
of 100 to 500 nm is deposited by chemical vapor deposition (CVD). Subsequently, as illustrated in
FIGS. 33 and 40
, the deposited oxide film
21
is etched (etching back) with strong anisotropy. As illustrated in these drawings, the oxide film
5
is left in different shapes depending on the space or distance between element forming regions
4
(transistor forming regions). As a result, transistor characteristics of each transistor are not always uniform, but different depending on the pattern of the transistor forming, regions
4
. More specifically, if the distance between the adjacent transistor forming regions is large, the oxide film
5
is shaped like a spacer. On the other hand, if the distance between the adjacent transistor forming regions is small, the oxide film
5
is in a buried or filled form.
Then, as illustrated in
FIGS. 34 and 41
, a gate insulating film
7
and a polysilicon
8
are formed. The gate insulating film
7
is 100 Å in thickness, and the polysilicon (poly-Si)
8
contains phosphorus of not less than 1×10
20
/cm
3
in concentration, and is 2000 Å in film thickness.
After forming the polysilicon
8
into a pattern of gate electrode leads, a resist is formed only on the PMOS region, and phosphorus ions of 1 to 3×10
13
/cm
2
are implanted at 40 KeV into the NMOS region, though not illustrated. This is the LDD doping for the NMOS FET. Next, a resist is formed only on the NMOS region, and boron ions of 1 to 3×10
13
/cm
2
are implanted at 20 KeV into the PMOS region, though not illustrated. This is the LDD doping for the PMOS FET.
After removing the resist on the NMOS region, an insulating film
9
is formed only on the side surface of the gate electrode
8
through the step illustrated in
FIGS. 35 and 42
. In this process, an insulating film is first deposited and then etched with strong anisotropy, whereby the insulating film
9
may be left self-conformably only on the side surface of the gate electrode
8
. Then, a resist is formed only on the PMOS region, and phosphorus ions of 4 to 6×10
13
/cm
2
are implanted at 40 KeV into the NMOS region as illustrated in
FIGS. 35 and 42
. This is the source/drain doping for the NMOS FET. Next, a resist is formed only on the NMOS region, and boron ions of 4 to 6×10
13
/cm
2
are implanted at 20 KeV into the PMOS region, though not illustrated. This is the source/drain doping for the PMOS FET.
Then, as illustrated in
FIGS. 36 and 43
, the interlayer insulating film
11
of 7000 Å in thickness is formed. A resist
18
a
is further applied thereon, in which contact holes are formed to communicate to the gate electrode
8
and source/drain
10
. Subsequently, as illustrated in
FIGS. 37 and 44
, a metal layer mainly composed of aluminum is formed by sputtering, and aluminum leads
12
are patterned. Thus, a SOI MOSFET is formed.
In the step illustrated above in
FIGS. 33 and 40
of the conventional manufacturing process, it is certain that desirable transistor characteristics are obtained, when the oxide film
5
is filled between two adjacent transistor forming regions
4
. When the oxide film
5
is shaped like a spacer, there is a disadvantage of a hump occurring in the subthreshold characteristic, resulting in an increase in leakage current.
FIG. 45
is a schematic view for explaining the cause of such a disadvantage. The spacers
5
are over-etched by etching back the oxide film
11
, and the spacers
5
are further etched by wet treatment for removing the oxide film prior to the gate formation, whereby an upper corner portion. (parasitic MOS) of each SOI element forming region
4
becomes exposed. As a result, the gate electric field is concentrated at the corner portions, and the threshold voltage is lowered, eventually resulting in occurrence of hump in the subthreshold characteristic.
Notwithstanding, the etching back of the oxide film
11
performed in the steps illustrated in
FIGS. 32
to
33
and
FIGS. 39
to
40
is an essential process. Without the etching back, the characteristics will deteriorate.
FIGS. 46
to
48
are schematic views explaining the mentioned disadvantages. That is, after etching the SOI layer
3
u

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