Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2001-08-03
2003-07-01
Chowdhury, Tarifur R. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S043000, C349S110000, C349S187000
Reexamination Certificate
active
06587165
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a thin film semiconductor device and a liquid crystal display unit, and fabrication methods thereof. In particular, the present invention concerns a gate interconnection structure and a light shield structure for thin film transistors integrated on a thin film semiconductor.
Thin film semiconductors, on each of which thin film transistors and pixel electrodes are integrated, are being widely used for substrates for driving liquid crystal display units. In particular, a thin film semiconductor device built in a liquid crystal display unit for a projector is essential to have a light shield structure for shielding thin film transistors from intensive light coming from a liquid source of the projector. One example of such a liquid crystal display unit is shown in FIG.
5
. As shown in this figure, the liquid crystal display unit uses a thin film transistor for driving each pixel electrode
8
. The thin film transistor is typically composed of a high temperature polysilicon TFT; however, it may be composed of a low temperature polysilicon TFT or an amorphous silicon TFT. The liquid crystal display unit shown in the figure is disclosed, for example, in Japanese Patent Laid-open No. Hei 2000-131716. As shown in the figure, the liquid crystal display unit includes a substrate
1
(quartz for supporting TFTs) having TFTs
7
as pixel transistors and a counter substrate
2
, with liquid crystal
3
held between the substrate
1
and the counter substrate
2
. The counter substrate
2
has a counter electrode
6
.
Referring to
FIG. 5
, the substrate
1
has a pixel electrode
8
in an upper layer portion, and a TFT (thin film transistor, which has a top gate structure herein) in a lower layer portion. The TFT
7
is used as a switching element for driving the pixel electrode
8
. The TFT
7
has, as an active layer, a semiconductor thin film
10
which is made from first layer polysilicon. A gate electrode G is formed on the semiconductor thin film
10
via a gate insulating film
11
made from SiO
2
. The gate electrode G is made from second layer polysilicon. The TFT
7
has a source region S and a drain region D on both sides of the gate electrode G. LDD regions
71
and
72
are formed at end portions of the source and drain regions, respectively. Extraction electrodes
12
A and
12
B are connected to the source region S and the drain region D, respectively. Each of the extraction electrodes
12
A and
12
B is made from an aluminum based material such as aluminum. The extraction electrode
12
A is electrically connected to the source region S of the TFT
7
via a contact hole SCN, and the extraction electrode
12
B is electrically connected to the drain region D of the TFT
7
via a contact hole DCN.
The semiconductor thin film
10
includes an auxiliary capacitance (Cs)
13
. The auxiliary capacitance (Cs)
13
is formed by holding a dielectric film made from, for example, SiO
2
forming the gate insulating film
11
between the first layer polysilicon forming the semiconductor thin film
10
, that is, the TFT
7
, and the second layer polysilicon forming a semiconductor thin film
14
, that is, the gate electrode G.
Light shield layers
4
M and
4
P are formed in an intermediate layer portion between the upper layer portion having the pixel electrode
8
and the lower layer portion having the TFT
7
. The light shield layers
4
M and
4
P are located on the counter substrate
2
side with respect to the TFT
7
, that is, on the light coming side, and therefore, they are called “upper side light shield layers”. That is to say, the upper side light shield layers herein are composed of the mask shield layer
4
M and the pad shield layer
4
P. With the aid of the two upper side light shield layers (mask shield layer
4
M and pad shield layer
4
P) and the extraction electrodes
12
A and
12
B (each of which is made from aluminum herein) overlapped to the upper side light shield layers, the overall pixel region except for a pixel opening is shielded from light coming from the counter substrate
2
side. Each of the mask shield layer
4
M and the pad shield layer
4
P is made from a conductive material, for example, a metal such as Ti. The mask shield layer
4
M is continuously patterned along the row direction (cross direction) of the pixels, and shields the TFT at least partially from external light. The pad shield layer
4
P is patterned discretely for each pixel, and contributes to the contact with the pixel electrode
8
. To be more specific, the pixel electrode
8
is connected to the pad shield layer
4
P via contact hole PCN. The pad shield layer
4
P is connected to the extraction electrode
12
B via a contact hole JCN. The extraction electrode
12
B is, as described above, connected to the drain region D of the TFT
7
via the contact hole DCN. By providing the mask shield layer
4
M and the pad shield layer
4
P and the extraction electrodes
12
A and
12
B overlapped to the shield layers
4
M and
4
P, the overall pixel region except for the pixel opening can be shielded from light coming from the counter substrate side.
On the other hand, a light shield layer
5
is formed on a portion, opposed to the counter substrate
2
side, of the pixel transistor portion. This light shield layer
5
is called “lower light shield layer”. At least the end portions of the source and drain of the pixel transistor
7
, and the LDD regions
71
and
72
are formed at the end portions of the source and drain thus shielded from external light. In general, the lower light shield layer
5
is made from a silicide of a refractory metal, such as WSi and has a thickness of 200 nm.
To satisfy recent strong demands toward higher luminance of a liquid crystal projector, the liquid crystal panel of the type shown in
FIG. 5
has been required to be improved in terms of its transmittance. At the same time, the liquid crystal panel shown in
FIG. 5
has been required to keep a high image quality even under a condition with a large quantity of light coming from a light source for a projector. To meet these market requirements for the liquid crystal panel of the type shown in
FIG. 5
, there have been adopted a method (1) of improving the transmittance by increasing the pixel opening rate, and a method (2) of keeping a high image quality by increasing the area of an auxiliary capacitance (Cs). The methods (1) and (2), however, are essentially inconsistent with each other. Namely, if the auxiliary capacitance (Cs) is increased, the pixel opening rate is reduced. The reason why the methods (1) and (2) have been simultaneously adopted is due to the fact that there has been a margin of the layout of pixels. However, along with tendency toward higher definition of a liquid crystal projector, it has been difficult to realize the layout of pixels with such a margin, and it has become impossible to achieve higher pixel opening rate on the basis of the related art pixel structure.
FIG. 6
is a schematic plan view of the prior art liquid crystal display unit shown in
FIG. 5
, particularly, one pixel region of the liquid crystal display unit. As shown in the figure, the liquid crystal display unit includes a plurality of signal interconnections
12
and gate interconnections crossing the signal interconnections
12
. Pixels are provided at crossing points between the signal interconnections extending to column direction (longitudinal direction) and the gate interconnections extending in the row direction (cross direction). As described above, the pixel includes the pixel electrode, the thin film transistor for driving the pixel electrode, and the light shield band (light shield layer) for shielding the thin film transistor from external light. The thin film transistor has, as the active layer, the semiconductor thin film
10
. The source region of the semiconductor thin film
10
is connected to the signal interconnection
12
via the contact hole SCN; the drain region thereof is connected to the pixel electrode (not shown) via the contact hole DCN; and
Hashimoto Makoto
Sato Takusei
Chowdhury Tarifur R.
Sonnenschein Nath & Rosenthal
Sony Corporation
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