Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1996-07-03
2001-12-04
Cuneo, K. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000
Reexamination Certificate
active
06326561
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a thin-film multilayer wiring board for being packaged in electronic devices or various types of electrical apparatus, and a process for producing such a wiring board.
For elevating the operating speed of computers, increase of signal transmission speed of the packaging module is an important factor.
Hitherto, a thick-film board comprising a ceramic substrate and a wiring layer principally made of W or Mo and formed on said ceramic substrate by a laminating and sintering method has been used as said module. Recently, however, attention is focused on a thin-film multilayer wiring board in which, in order to realize speed-up of signal transmission, a polyimide film with a low dielectric constant is formed as an interlaminar insulating film on the ceramic substrate, and a conductive layer is made of a highly conductive substance such as Cu, Al, Au or the like.
In recent years, however, computer performance has advanced rapidly and the number of the packaged gates has increased remarkably, entailing the necessity of increasing the number of the wiring layers in the thin-film wiring system.
Several proposals have been made on the thin-film multilayer wiring techniques, wherein a successive laminating system is generally employed. This system comprises forming a conductor layer made of Cu, Al or the like on a ceramic or Si substrate, forming via holes therein, conducting insulating layer patterning by photolithography, and making electrical connections.
Techniques for forming via holes or through-holes of 100 &mgr;m or less in diameter are needed for said interlaminar connection. Also, fine patterns with a line width or space width of 20-50 &mgr;m are necessary for thin-film wiring. For instance, it is required to lay 2-5 wires between the 150-500 &mgr;m connecting pads. In this case, the via hole diameter needs to be about 20-30 &mgr;m. However, the limit of the hole diameter that can be formed by the currently available drilling techniques is about 70 &mgr;m, and other means must be applied for forming the holes of smaller diameters.
Recently, attention is drawn to laser working and dry etching as suitable methods for forming fine holes such as mentioned above. Both methods are excellent in fine working, but a difference is seen between them in shape of the holes formed.
It is known that the method using excimer laser is an excellent working method for forming fine via holes or through-holes (JP-A-60-261685). However, he projected shape of the hole formed thereby tends to taper down toward the end (base) with an angle of about 20 to 30° against the axis of the hole.
As a method that can eliminate the above problem, a so-called conformal mask method—a method in which laser working is performed through a mask comprising a metallic film having openings at the pattern portion of an organic insulating layer where holes are to be formed—is effective. According to this method, as shown in
FIG. 2
, the hole formed has a taper angle (&thgr;) of about 15-5° against the axis of the hole when the energy density of the excimer laser is 300 to 1,000 mJ/cm
2
. Thus the tapering phenomenon toward the end (base) can be suppressed to a considerable degree. The result of the tests conducted by the present inventors shows that the taper angle &thgr; of the hole formed is reduced and its straightness is enhanced proportionally as the energy density increases.
On the other hand, as opposed to said laser working, according to dry etching using oxygen plasma controlled to a low gas pressure (for example, 5 Pa or less), it is possible to form an almost straight hole with a taper angle (&thgr;) less than 5°. It was found from a series of experiments that when the plasma gas pressure becomes higher than 5 Pa in dry etching of an organic insulating layer such as a polyimide layer, the hole formed is curved in section like a barrel.
Such drying etching techniques have been used for wiring or patterning of the insulating layers in the LSI semiconductor manufacturing processes. For instance, a method for forming the contact holes in the interlaminar insulating layer on a semiconductor substrate by dry etching using a reactive gas (a mixed gas of CF
4
, CHF
3
, Ar, O
2
, Cl, etc.) is disclosed in JP-A-4-150023 and JP-A-5-121371. In the former, the etching gas pressure for forming a straight hole is specified to be 0.6 Torr or below (80 Pa or below) while in the latter, the etching gas pressure is defined to be 10 to 50 m Torr (1.33 to 6.65 Pa).
SUMMARY OF THE INVENTION
An object of the present invention is to provide a thin-film multilayer wiring board in which the upper and lower wiring layers of the board are connected by the via studs produced by filling a conductive metal in the fine via holes having a specific diameter (for example, 70 &mgr;m or less) formed in an organic insulating layer, and a process for manufacturing such a wiring board.
The present invention provides a thin-film multilayer wiring board comprising a first and a second metallic wiring layers formed on a substrate with an organic insulating layer interposed between the metallic wiring layers, wherein the lands of said first and second metallic wiring layers are electrically connected by via studs which are made of a conductive metal filled in via holes and formed by electroless plating, and if necessary, further comprising one or more metallic wiring layers interposing one or more organic insulating layers therebetween alternately and electrically connected to each previously formed metallic wiring layer by via studs formed in the same manner as mentioned above.
The present invention also provides a thin-film multilayer wiring board comprising a first and a second metallic wiring layers formed on a substrate with an organic insulating layer interposed between the metallic wiring layers, wherein the lands of said first and second metallic wiring layers are electrically connected by via studs which are made of a conductive metal filled in via holes and formed by electroless plating, and the difference between the top end diameter and the base diameter of said via studs is 10% or less, or the angle made by the taper of the insulating layer interface of each via stud with the axis thereof is 5° or less, and if necessary, further comprising one or more metallic wiring layers interposing one or more organic insulating layers therebetween alternately and electrically connected to each previously formed metallic wiring layer by via studs formed in the same manner as mentioned above.
The present invention further provides a process for producing a thin-film multilayer wiring board which comprises
attaching an insulating adhesive sheet to a substrate having a first metallic wiring layer on its surface to form an insulating layer,
forming via holes in said insulating layer by dry etching or laser working,
filling said via holes with a conductive metal by electroless plating to form via studs,
grinding out the portions of said via studs projected from the insulating layer to make said insulating layer surface flat, and
forming a second metallic wiring layer on said insulating layer and connecting it to said via studs, and if necessary, repeating the step of attachment of an insulating adhesive to the step of formation of a second metallic wiring layer a plurality of times.
The present invention still further provides a process for producing a thin-film multilayer wiring board, which comprises the steps of
(1) laminating a composite sheet comprising a carrier sheet and an adhesive layer on a substrate having a first metallic wiring layer on the surface thereof so as to contact the adhesive layer with the first metallic wiring layer;
(2) removing said carrier sheet and hardening the adhesive layer to form an insulating layer;
(3) forming via holes in said insulating layer;
(4) filling said via holes with a conductive metal by electroless plating;
(5) grinding out projected portions of the conductive metal from the-surface of said insulating layer to flatten the conductive metal and to form
Imai Tsutomu
Itabashi Takeyuki
Miura Osamu
Ookoshi Yukio
Suzuki Hitoshi
Antonelli Terry Stout & Kraus LLP
Cuneo K.
Hitachi , Ltd.
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