Thin-film electrical connections for integrated circuits

Details Thin-film electrical connections for integrated circuits Thin-film electrical connections for integrated circuits

1985-01-31

1987-11-10

Tufariello, T. M.

Chemistry: electrical and wave energy

Processes and products

204 384, C25D 502

Patent

active

047056061

ABSTRACT:
A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over the entire surface of the substrate covering the pattern of thin-film metallic interconnect lines. A portion of the dielectric layer is then removed to expose the thin-film metallic interconnect lines so that a series of trenches is formed above each interconnect line. The interconnect lines are then electroplated to form a series of thicker metal interconnect lines such that the thicker metal interconnect lines and the dielectric layer form a substantially planer surface. This process can then be repeated in its entirely to form a plurality of interconnect signal planes. In the preferred embodiment, metallic vias are provided between each layer of metallic interconnect lines for electrical connection purposes.

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Lewis, "High-Density High-Impedance Hybrid Circuits . . . ", IEEE Transactions on Components, Hybrids, and Mfg. Tech., CHMT-2, #4, (1979), 441-450.
Moriya et al., "High-Density Multilayer Interconnection with Photo-Sensitive . . . ", 1984 Proceedings of the 34th Elec. Components Conf., (1984), 82-87.

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