Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2002-03-01
2004-07-27
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S668000, C257S700000, C257S701000, C257S773000, C257S698000, C257S730000
Reexamination Certificate
active
06768205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an electronic device, and especially relates to a thin-film circuit substrate that has through holes, and a manufacturing method thereof and a via formed substrate that has through holes, and a manufacturing method thereof.
A so-called via formed substrate that has a large number of through holes formed is an important component for an interposer type part, a multilayer circuit board, and three-dimensional chip mounting technology.
Various circuit patterns are formed on the via formed substrate. In the interposer type component inserted between a wiring substrate and an LSI chip, a supply voltage fluctuation due to a high-speed operation of the LSI chip can be absorbed by forming a high dielectric capacitor or a ferroelectric capacitor on the substrate.
Further, by installing a via formed substrate such as above on a package substrate with other parts, a system package can be formed, and a multi chip module (MCM) and a system-in-package can be formed by arranging various parts, including an LSI chip, on the via formed substrate.
2. Description of the Related Art
Conventionally, via formed substrates using a ceramic substrate as a base have been marketed. In the via formed substrates available in the market, a number of through holes are formed on the ceramic substrate, each through hole being provided with a via plug of a low resistance metal, such as Cu and W.
FIG.
1
(A) and FIG.
1
(B) show an example of a plan and a cross section, respectively, of a conventional via formed substrate.
With reference to the plan of FIG.
1
(A), a number of via holes
12
A are formed in a ceramic substrate
11
that is made of Al
2
O
3
and the like, and each via hole
12
A is filled with a via plug
12
B that is made of a metal such as Cu and W.
The via formed substrate as shown in FIG.
1
(A) and FIG.
1
(B) is designed so that it is mainly inserted between a wiring substrate and electronic parts, and a number of electrode pads
13
which are made of nickel etc. are formed corresponding to each via plug
12
B as shown in the cross section drawing of FIG.
1
(B). By forming a solder vamp on each of the electrode pads
13
, the via formed substrate electrically connects the wiring substrate on the bottom side and electronic parts on the top side.
FIG. 2
shows an example of an interposer type thin-film circuit substrate of the related technology, in which a thin-film circuit including a ferroelectric capacitor is formed on the via formed substrate. In the interposer type thin-film circuit substrate in which this ferroelectric capacitor is formed, power supply wiring can be formed directly under an LSI chip in the shortest distance, and an impedance of the power supply wiring is minimized. Consequently, a power supply voltage fluctuation due to a high-speed operation of the LSI chip is suppressed by using the interposer type thin-film circuit substrate.
With reference toy
FIG. 2
, the electrode pads
13
of the upper surface of the via formed substrate
11
of FIG.
1
(B) are removed by polish processing, and a capacitor insulator layer
14
of a material such as a ferroelectric material and a high dielectric material, such as BST and PZT, is formed on the upper surface of the via formed substrate
11
. On the capacitor insulator layer
14
, a metal layer
15
that functions as a grounding electrode is formed, and a polyimide protective coat
16
is further formed on the metal layer
15
.
Contact holes penetrate the metal layer
15
, the capacitor insulator layer
14
and the polyimide protective coat
16
, exposing an edge of the via plugs
12
B, and contact plugs
17
A are formed, filling up the contact holes. Further, electrode pads
17
B are formed on the polyimide protective coat
16
, contacting a tip of the contact plugs
17
A.
Vamp electrodes
18
, such as solder balls, are formed on the electrode pads
17
B. On the undersurface of the via formed substrate
11
, vamp electrodes
19
, such as solder balls, are formed under the electrode pads
13
.
As regards parts including a capacitor insulator layer of a material such as a ferroelectric material and high dielectric material, heat treatment in an oxidization atmosphere at a temperature of at least 700 degrees C. is necessary. Since the via plugs
12
B in the via holes
12
A are made of a metal such as Cu and W which are easy to oxidize, the via plugs
12
B expand as a result of oxidization, causing destruction of the thin film circuit formed on the surface of the ceramic substrate
11
. In addition, control of contraction accompanying sintering when producing ceramic substrates is difficult, making it difficult to mount an LSI with large integration density on a via substrate using the ceramic substrate.
On the other hand, it is conceivable that an Si substrate is used as a via formed substrate, and minute via holes are arranged in a fine pitch on the Si substrate by a semiconductor process. Especially, by using a dry etching process, it is possible to form a large number of minute via holes simultaneously, having an extraordinarily large aspect ratio, in a fine pitch into the Si substrate.
In the dry etching process, however, an etching rate generally tends to vary, causing via holes to form with different depths when forming a large number of deep via holes, the variance being around ±5%. Consequently, when the dry etching process for a predetermined period is finished, some via holes may not have completely penetrated the Si substrate.
In this concern, when forming deep via holes in an Si substrate by dry etching, it is necessary to polish the back surface of the substrate after the dry etching process such that all the via holes surely have opening. Moreover, a needle-like structure is easy to be formed in a via hole bottom when forming a deep via hole in an Si substrate by dry etching. It is, therefore, considered indispensable to polish the back surface of the substrate as described above. The polishing process increases production costs of a via formed substrate.
Further, in the case of the via formed substrate based on the Si substrate, further polishing process is necessary in order to remove a surplus metal layer after filling up the via holes with a low resistance metal, such as Cu and W, and the polishing of the substrate surface has to be to a mirror finish so that a thin film circuit can be formed. Such mirror polishing further increases the production cost of the via formed substrate. Moreover, a process for forming an insulator layer on the mirror-polished surface of the via formed substrate is necessary prior to forming a thin-film circuit.
Further, in the via formed substrate based on the Si substrate, which is formed in this manner, when a thin-film circuit including a capacitor, such as a ferroelectric capacitor and a high dielectric capacitor, is formed on a via formed substrate, the via plugs in the via holes oxidize through the heat treatment in an oxidization atmosphere, causing the destruction or damage of the thin-film circuit, similar to the case of the via formed substrate of the conventional ceramic substrate. Moreover, the heat treatment for forming the thin-film circuit including the ferroelectric or the high dielectric capacitor can cause the via plugs to shrink.
Accordingly, it is desired that a thin-film circuit substrate, solving the problems as above be offered, which is based on the via formed substrate in which the via holes are formed in the Si substrate.
With an advancement in the integration density of LSI, and an enhancement of functions, need for decreasing the pitch of via holes in a substrate for mounting LSI, such as an MCM substrate using a via formed substrate, is rising.
Since via holes have been formed by machining, there is a limit to reduction in the pitch of the via formed substrate of the conventional technology, such as a ceramic substrate and a resin substrate. The limit can be eliminated by using an Si substrate as a via formed substrate, and by forming the via holes through
Imanaka Yoshihiko
Miyashita Tomoko
Omote Koji
Taniguchi Osamu
Yamagishi Yasuo
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Williams Alexander Oscar
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