Thin core substrate for fabricating a build-up circuit board

Details Thin core substrate for fabricating a build-up circuit board Thin core substrate for fabricating a build-up circuit board

2001-04-20

2003-06-10

Hail, III, Joseph J. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S825000, C029S830000, C029S852000

Reexamination Certificate

active

06574863

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method of fabricating a multilayer circuit board. More particularly, the present invention relates to a build-up type multilayer circuit board made involving the use of a thin core substrate, on which a stack of thin layers, alternatively insulating and conductive, are deposited and electrically conductive via holes are formed in the insulating layers to provide electrical interconnections among the conductive layers.
2. Description of the Related Art
The desirability of miniaturization of electronic products has long been known, especially for those electronic products, to name just a few, such as cellular phones, hand carry computers, hand carry camcorders, personal digital assistants, etc. These electronic products currently require circuit boards and electronic components to be smaller and thinner than ever before. Following such a trend, there is also a demand to mount the semiconductor elements on a circuit board at a high mounting density. For this end, incorporating the thin and high wiring density multilayer circuit boards into electronic products has thus created many challenges to the circuit board designers and manufacturers.
In the circuit board manufacturing industry, there is continuous pressure to provide a low cost, high reliability and high wiring density circuit board. To accomplish this, the build-up technique has been developed. The so-called build-up technique is basically meant to involve the fabrication of a stacking of thin layers, alternatively insulative and conductive, combined with conductive via holes for interconnecting the different thin conductive layers on a core substrate (or say core circuit board). The number of layers built up can be further increased to more than ten or twenty layers to meet the needs in some applications in the current electronics industry. To date, the build-up circuit boards made by the build-up technique have already been incorporated within a variety of electronic devices in a number of commercial products.
In general, to produce a build-up multilayer circuit board, a single-sided, two-sided board or multilayer board may be used as the core substrate. The typical prior art build-up multilayer circuit boards are illustrated in
FIGS. 1 and 2
. Referring to
FIG. 1
, the build-up multilayer circuit board
100
includes a core substrate
101
and a build-up structure
102
. The core substrate
101
comprises several patterned conductive layers
103
and an insulating layer
104
formed in between any two adjacent conductive layers
103
. A conductive through-hole
105
is made to electrically interconnect the patterned conductive layers
103
. The build-up structure
102
comprises the multiple layers of the patterned conductive layers
106
and insulating layers
107
, however, commonly which are much thinner than the conductive layers
103
and insulating layers
104
present in the core substrate
101
. The vias
108
are formed to electrically interconnect any two adjacent conductive layers
106
within the build-up structure
102
. As seen in this example, the core substrate
101
is a multilayer (i.e. six layers) circuit board and the build-up structure
102
has two build-up layers.
Another example of the prior art build-up circuit boards is shown in
FIG. 2
, in which the build-up circuit board
200
includes a circuit board
201
and a build-up structure
202
. The circuit board
201
comprises two patterned conductive layers
203
and one insulating layer
204
located in between the conductive layers
203
. A conductive through-hole
205
is made to electrically interconnect the two conductive layers
203
. The build-up structure
202
comprises the multiple layers of the patterned conductive layers
206
and insulating layers
207
, which are commonly much thinner than the conductive layers
203
and insulating layers
204
present in the core substrate
201
. The vias
208
are formed to electrically interconnect any two adjacent conductive layers
206
within the build-up structure
202
. As seen in this example, the circuit board
201
is a multilayer (i.e. two layers) circuit board and the build-up structure
202
has two build-up layers on both sides of the core substrate
201
, which results in a six-layer circuit board.
In fabricating reliable vias for multilayer circuit boards, currently, there are three types of conductive vias that are prevailing in the industry as shown in FIG.
3
. In
FIG. 3A
is illustrated a so-called plated through hole, in which the via opening extends through the insulating layer
301
and the conductive layers
302
and
303
on both sides of the insulating layer
301
and a conductive layer of plated metal
304
is formed through the via opening. The recess created by the via after plating is filled with a conductive or non-conductive filled material
305
to assure a reliable electrically conductive through hole that is fabricated.
Another further form of the vias is shown in
FIG. 3B
, in which the via opening extends through the insulating layer
306
but does not extends through the conductive layer
307
. After a plated layer
308
is deposited, the recess created by the via is filled with a conductive or non-conductive material
309
to obtain the good planarity for the next processing step.
The third form of the vias fabricated is illustrated in
FIG. 3C
, in which the via opening extends through the insulating layer
310
but does not extends through the conductive layer
311
. After the via opening is completely filled with a conductive material
313
, a circuit layer
312
is formed.
As seen, these all three types of the vias require a process of filling a filled material into the recess created by the via, however, which will become infeasible when the via diameter less than 0.05 millimeter. However, in current technological environment, the above three types of the vias used for fabricating a build-up multilayer circuit board, the via diameter should be larger than 0.1 millimeter for facilitating the mass production. Under such a condition, the core substrate made with the use of those conductive vias described will be subjected to a limitation to achieve a further higher wiring density.
It is therefore desirable to provide a thin core substrate having a further higher wiring density for making a further thinner and higher wiring density build-up multilayer circuit board.
SUMMARY OF INVENTION
It is therefore an objective of the present invention to provide a thin core substrate for making a thin and high wiring density build-up multilayer circuit board.
Another objective of this invention is to adopt a method for making a core substrate. The method involves the use of an insulating layer which is covered with the electrically conductive sheets. The openings are made in the electrically conductive layers at the predetermined positions, where the vias are also formed in the insulating layer. An electrically conductive layer is deposited to cover the vias. After the electrically conductive sheets and layer are patterned, a core substrate is constructed.
Another further object is to prepare a thin core substrate for fabricating a build-up multilayer circuit board. The method involves the use of an insulating layer which is covered with the electrically conductive sheets. The openings are made in the electrically conductive layers at the predetermined positions, where the vias are also formed in the insulating layer. An electrically conductive layer is deposited to cover the vias. After the electrically conductive sheets and layer are patterned, a thin core substrate is constructed. Afterwards, the build-up layers are made at least one side of the thin core substrate to form a build-up multilayer circuit board.


REFERENCES:
patent: 4642160 (1987-02-01), Burgess
patent: 4915983 (1990-04-01), Lake et al.
patent: 5567329 (1996-10-01), Rose et al.
patent: 5747358 (1998-05-01), Gorrell et al.
patent: 5786270 (1998-07-01), Gorrell et al.
patent: 6005198 (1999-12-01), Gregoire

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