Thickened sidewall dielectric for memory cell

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S261000, C438S435000, C438S259000

Reexamination Certificate

active

08058140

ABSTRACT:
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

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