Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2002-02-15
2004-12-14
Deo, Duy-Vu (Department: 1765)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S396000, C257S243000, C257S300000
Reexamination Certificate
active
06830984
ABSTRACT:
BACKGROUND OF THE INVENTION
a. Field of the Invention
The present invention pertains generally to the processing of integrated circuits and more specifically to the processing of copper integrated circuits.
b. Description of the Background
As the density of components increase on an integrated circuit, the supply of power becomes more critical to the proper functioning of the device. As the power supply needs increase, the size of the power supply traces need to increase as well.
With conventional processing methods of integrated circuits, there is a practical limit to the thickness of the trace. Additionally, the width of a trace can be limited by processing limitations and by the available planar area or real estate available. Such limits force a designer to dedicate more than one layer of traces to one specific power supply path, placing vias in between the multiple layers. Such a design requires several processing steps to complete the manufacturing process and thereby increases the cost of the integrated circuit.
Several types of components, such as capacitors and inductors, are difficult to manufacture using existing processing techniques. These devices are limited in their performance by the thickness of the traces from which they are fabricated.
It would therefore be advantageous to provide designs and methods of fabrication for thick circuit traces. It would further be advantageous to provide thick traces at lower processing costs than conventional designs. Thick traces may also enhance the performance of capacitors and inductors in integrated circuits.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages and limitations of the prior art by providing a method for the creation of special thick traces. The thick traces may reduce the processing time and thus cost of the fabrication of integrated circuits as several steps may be eliminated. Further, the thick traces may be formed by using a photomask reticule more than once, reducing the tooling cost for an integrated circuit.
Certain components may be fabricated using the inventive thick traces. For example a capacitor may be fabricated in an integrated circuit with enhanced capacitance and greater performance. Inductors may likewise be created that have increased inductance using the inventive thick traces.
The present invention may therefore comprise a method for forming a thick signal trace in an integrated circuit comprising: forming a first layer of dielectric; etching the first layer of dielectric to form a first trench using a first pattern; filling the first trench with a conductive material to form a first electrical trace having a top surface; forming a second layer of dielectric; etching the second layer of dielectric to form a second trench using a second pattern, the second trench substantially fully exposing the top surface of the first electrical trace; and filling the second trench with the conductive material forming a second electrical trace having a bottom surface substantially conterminous with the top surface of the first trace.
The present invention may further comprise a trace in an integrated circuit formed by a process that comprises: forming a first layer of dielectric; etching the first layer of dielectric to form a first trench; filling the first trench with an encapsulating material; filling the first trench with a conductive material to form an electrical trace having a top surface; forming a second layer of dielectric; etching the second layer of dielectric to form a second trench, the second trench substantially exposing the top surface of the electrical trace; filling the second trench with encapsulating material; filling the second trench with the conductive material forming a second electrical trace having a bottom surface substantially coterminous with the top surface of the electrical trace; and covering the conductive material with the encapsulating material.
The present invention may further comprise a power trace in an integrated circuit comprising: a first conductor being formed in an dielectric layer and having a top surface, the first conductor having an encapsulant formed on the bottom and sides of the first conductor; a second conductor, the second conductor having a bottom surface formed conterminous with the top surface of the first conductor, the second conductor having an encapsulant formed on the bottom and sides of the second conductor; the dielectric material being selected to effect the capacitive coupling of the power trace.
The present invention may further comprise a capacitor in an integrated circuit comprising: a first signal trace and a second signal trace fabricated in at least one signal layer, the signal layer having a first dielectric material having a first dielectric material; at least two electrodes, each electrode being formed in a plurality of successive electrode layers comprising a second dielectric material; the electrodes being comprised of conductors formed in said successive layers, each of the conductors having a top surface and a bottom surface wherein the bottom surface is conterminous with the top surface for each of the successive layers; and wherein the first signal trace and the second signal trace are connected to alternating electrodes.
The present invention may further comprise an inductor in an integrated circuit comprising: successive layers comprising a top layer, at least one intermediate layer, and a bottom layer; the intermediate layer comprising a plurality of concentric loops, each loop being disunited at two points substantially opposite each other; the loops being comprised of conductors formed in the successive layers, each of the conductors having a top surface and a bottom surface wherein the bottom surface is conterminous with the top surface for each of the successive layers; and the top layer further comprising at least one trace connecting at least two of the concentric loops.
The present invention may further comprise an inductor in an integrated circuit comprising: a coiled trace formed in a plurality of successive layers, the coiled trace being comprised of conductors in successive layers, each of said conductors having a top surface and a bottom surface wherein the bottom surface is conterminous with the top surface for each of the successive layers, the layers further comprising a first non-conductive material, the coiled trace having a first end and a second end; a first signal trace and a second signal trace in a signal layer, the signal layer comprising a second non-conductive material; the first signal trace being in electrical communication with the first end of the coiled trace; and the second signal trace being in electrical communication with the second end of the coiled trace.
The advantages of the present invention are that increased power capacity in power supply traces may be achieved with a minimum of processing steps. Further, higher performance capacitors and inductors may be created using conventional processing steps.
REFERENCES:
patent: 6649464 (2003-11-01), Lee
patent: 6670237 (2003-12-01), Loh et al.
patent: 6680514 (2004-01-01), Geffken et al.
patent: 6680520 (2004-01-01), Voldman et al.
patent: 6680542 (2004-01-01), Gibson et al.
patent: 6710425 (2004-03-01), Bothra
patent: 6734477 (2004-05-01), Moise et al.
Schultz Richard T.
Wright Peter J.
Cochran Freund & Young LLC
Deo Duy-Vu
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