Thick oxide P-gate NMOS capacitor for use in a phase-locked...

Details Thick oxide P-gate NMOS capacitor for use in a phase-locked... Thick oxide P-gate NMOS capacitor for use in a phase-locked...

2001-12-27

2004-12-07

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C327S157000, C327S558000

Reexamination Certificate

active

06828654

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to a thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and methods for making the same.
2. Background Art
A phase-locked loop (PLL) synthesizer circuit is a negative feedback circuit that operates so as to bring a set frequency into conformity with an output signal frequency. PLL synthesizer circuits are used for automobile telephones, portable telephones, radios, televisions, cable modem tuners, and the like. As circuit integration and the desire for faster circuits increase, circuit designers are faced with new challenges to implement known functionality, such as in ability to maintain lock in a PLL synthesizer circuit.
An example of a conventional PLL synthesizer circuit will be explained with reference to
FIGS. 1-3
of the accompanying drawings. A quartz oscillator
102
outputs a reference clock signal “CK” of a natural frequency based on the oscillation of a quartz oscillation element to a reference frequency divider
104
. The reference frequency divider
104
divides the frequency of the reference clock signal CK on the basis of a set frequency, which is externally set, predetermined, or is otherwise programmed, and outputs a reference signal “fr” to a phase comparator
106
. A comparison frequency divider
108
outputs a comparison signal “fp” to the phase comparator
106
. The phase comparator
106
compares the reference signal fr with the comparison signal fp, and outputs pulse signals “&phgr;R” and “&phgr;P”, which correspond to the frequency difference and phase difference, respectively, to a charge pump
110
.
The charge pump
110
outputs a signal “SCP” (charge pump signal) on the basis of the pulse signals &phgr;R, &phgr;P output from the phase comparator
106
, to a low-pass filter (hereinafter referred to as “LPF”)
112
. This output signal SCP contains pulse component in its D.C. component. The D.C. component rises and falls with the frequency changes of the pulse signals &phgr;R, &phgr;P, while the pulse component changes on the basis of the phase difference of the pulse signals &phgr;R, &phgr;P.
The LPF
12
smooths the output signal SCP of the charge pump
110
, and outputs a signal “SLPF” (LPF signal), from which a radio frequency (RF) component is removed, to a voltage controlled oscillator (hereinafter referred to as “VCO”)
114
. The VCO
114
outputs a signal “SVCO” (VCO signal) having a frequency corresponding to the voltage value of the output signal SLPF of the LPF
112
to an outside circuit (not shown) and to the comparison frequency divider
108
described above. The comparison frequency divider
108
divides the frequency of the output signal SVCO of the VCO
114
by a necessary factor and outputs it to the phase comparator
106
.
As shown in
FIG. 2
, an unlock condition results when a setting of the comparison signal fp, for example, is changed such that the frequency and/or phase of the reference signal fr are not in conformity with those of the comparison signal fp. When these differences in the frequencies and phases of the reference signal fr and the comparison signal fp occur, the phase comparator
106
outputs the pulse signals &phgr;R and &phgr;P. The D.C. component of the output signal SCP of the charge pump
110
is passed by LPF
112
. The voltage level of the output signal SLPF of the LPF
112
rises on the basis of the output signal SCP, and the output signal SLPF of the LPF
112
converges to a voltage level corresponding to the comparison signal fp set afresh, and the operation mode returns to the lock state.
When the frequency of the comparison signal fp of the PLL synthesizer circuit is lowered as described above, the output signal SLPF of the LPF
112
rises from V
1
to V
2
as indicated by a solid line in
FIG. 3
, for example. However, since the phase difference occurs even when the frequency of the reference signal fr is in conformity with that of the comparison signal fp, the output signal SLPF, which has risen to a point near V
2
, converges with V
2
while repeating an over-shoot and under-shoot.
Prior art integrated versions of the PLL of
FIG. 1
typically implement the LPF
112
using a simple RC circuit. The capacitor of the RC circuit has comprised a PMOS FET (P-type metal oxide semiconductor field effect transistor).
FIG. 4
is a schematic diagram of a PMOS FET configured as a capacitor. The capacitance is formed by the gate capacitance and the depletion capacitance in series. If the transistor is in the strong inversion mode (V
GS
>V
TH
), the gate capacitance is the sole contributor of the total capacitance.
The gate capacitance is inversely proportional to the thickness of the gate oxide. As the technology advances, the thickness of the gate oxide of the transistor decreases, thus increasing the capacitance. However, a decrease of the gate oxide thickness causes the leakage current through the gate to increase. In the LPF
112
of the PLL circuit in
FIG. 1
, the gate voltage across the capacitor is used to control the VCO
114
which outputs the desired frequency SVCO. If there is gate leakage in the PMOS FET capacitor, the control voltage will not be held constant and will cause drift in the output frequency of VCO
114
.
What is needed is a technique to obtain a stable a PLL control voltage, without drastically increasing the complexity and cost of the circuit.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a phase locked loop circuit. The circuit includes an oscillator to output a reference clock signal; a reference frequency divider to receive and divide the reference clock signal, and output a reference signal; a comparison frequency divider to receive a control voltage and output a comparison signal; a phase comparator to receive the reference signal and the comparison signal, wherein the phase comparator compares the reference signal with the comparison signal and outputs a frequency difference signal and a phase difference signal; a charge pump to receive the frequency difference and the phase difference signals and output a charge pump signal; a low-pass filter to receive the charge pump signal and output a low pass filter signal; and a voltage controlled oscillator to receive the low pass filter signal and output the control voltage signal. The low-pass filter comprises a capacitor formed by an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P
+
gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P
+
pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line.
In another embodiment of the present invention, a low-pass filter for a phase locked loop (PLL) circuit includes a capacitor, comprising: an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P
+
gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P
+
pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. A gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the PLL.
In yet another embodiment according to the present invention, a semiconductor device, functioning as a capacitor, comprises an N-type substrate, a P-type region formed on the N-type substrate, a thick oxide formed over the P-type region, a P
+
gate electrode formed over the thick oxide and coupled to a first voltage supply line, and P
+
pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line.
These and other advantages and features will become readily apparent in view of the following.


REFERENCES:
patent: 4042945 (1977-08-01), Lin et al.
patent: 4249194 (1981-02-01), Rogers
patent: 4335359 (1982-06-01), Kriedt et al.
patent: 4377029

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