Thick metal layer integrated process flow to improve power...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead

Reexamination Certificate

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C257S778000, C257S758000

Reexamination Certificate

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06977435

ABSTRACT:
A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

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