Thermally improved semiconductor QFN/SON package

Details Thermally improved semiconductor QFN/SON package Thermally improved semiconductor QFN/SON package

2011-01-04

2011-01-04

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S106000, C438S123000, C438S124000, C257SE33066, C257SE23031, C257SE33059, C257SE23013, C257SE21502

Reexamination Certificate

active

07863103

ABSTRACT:
A semiconductor device without cantilevered leads uses conductive wires (120) to connect the chip terminals to the leads (110), and a package compound (140) to encapsulate the chip surface (101a) with the terminals, the wires, and the lead surfaces with the attached wires. The chip surface (101b) opposite the terminals together with portions (103) of the chip sidewalls protrude from the package, allowing an unimpeded thermal contact of the protruding chip surface to a substrate (201) to optimize the thermal flux from the chip to the substrate. Solder bodies (250) attached to the compound-free lead surfaces (113b) can be connected to the substrate so that the solder bodies are as elongated as the protruding chip height, facilitating the void-free distribution of an underfill compound into the space between chip and substrate, and improving the absorption of thermomechanical stresses during device operation.

REFERENCES:
patent: 5339518 (1994-08-01), Tran et al.
patent: 6617193 (2003-09-01), Toshio et al.
patent: 2007/0190694 (2007-08-01), Punzalan et al.
patent: 2009/0166824 (2009-07-01), Do et al.
patent: 2009/0166826 (2009-07-01), Janducayan et al.

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