Thermally enhanced semiconductor device having exposed backside

Details Thermally enhanced semiconductor device having exposed backside Thermally enhanced semiconductor device having exposed backside

1994-01-10

1995-09-12

Thompson, Gregory D.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

174 163, 174 522, 257706, 257787, 361714, 361717, 361722, H05K 720

Patent

active

054502837

ABSTRACT:
A thermally enhanced semiconductor device (10) having an exposed backside (22) is described. In one embodiment, a PC board substrate (12) is provided having a pattern of conductive traces (14) on both upper and lower surfaces of the substrate. Electrical continuity is maintained between the two surfaces with conductive vias (16). A semiconductor die (18) is flip-mounted to the upper surface of the substrate. Solder bumps (26) electrically connect the die to the conductive traces, and an underfill (28) couples the active side (20) of the die to the upper surface of the substrate. A package body (40) is formed around the perimeter (24) of the die leaving the inactive backside exposed for enhanced thermal dissipation. The inactive backside can also be coupled to a heat sink for increased thermal dissipation. A plurality of solder balls (42) electrically connected to the conductive traces is attached to the lower surface of the substrate.

REFERENCES:
patent: 4604644 (1986-08-01), Beckham et al.
patent: 4825284 (1989-04-01), Soga et al.
patent: 4970575 (1990-11-01), Soga et al.
patent: 4987100 (1991-01-01), McBride et al.
patent: 5107325 (1992-04-01), Nakayoshi
patent: 5177669 (1993-01-01), Juskey et al.
patent: 5222014 (1993-06-01), Lin
patent: 5239198 (1993-08-01), Lin et al.
patent: 5249101 (1993-09-01), Frey et al.
patent: 5291062 (1994-03-01), Higgins, III
patent: 5311402 (1994-10-01), Kobayashi et al.

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