Thermally efficient semiconductor chip

Details Thermally efficient semiconductor chip Thermally efficient semiconductor chip

2000-06-22

2001-09-18

Tolin, Gerald (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C165S185000, C257S713000, C361S719000

Reexamination Certificate

active

06292367

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to heat sinks for semiconductor chips and, more particularly, to a semiconductor chip and heat spreading structure to efficiently conduct away the heat generated by the semiconductor chip.
2. Description of the Related Art
Electronic devices and systems, such as computers, consist of semiconductor chips containing integrated circuits and other electronic components, which are mounted on a substrate. With the demand for higher levels of integration in semiconductor chips, more and more circuits are incorporated in the semiconductor chips. This higher level of integration coupled with a reduction in the dimensions of the device or transistor of the integrated circuit produces a semiconductor chip which generates a substantial amount of heat during operation. In addition, the transistors of the integrated circuit are being fabricated to operate faster which further increases the amount of heat generated during operation. One known technique for assisting in reducing heat generated by integrated circuits with the same power during operation of the semiconductor chip is to form a high conductivity layer, such as silicon carbide and diamond, on or adjacent the back of the chip.
However, in scaling down the device size, with advances in lithographic techniques, to increase the number of integrated circuits requires that such a chip contain both low power and high power circuits. Because of this requirement, the heat generated across such a chip is not uniform since the high power circuits generate more heat than the low power circuits and create “hot spots” in the chip. These localized “hot-spots” in the chips result in a non-uniform temperature across the chip which causes excessive chip stresses and can lead to chip failure.
Consequently, there exits a need for thermal solutions that limits the maximum chip temperature and provides an uniform chip temperature across the high/low power integrated circuit chip areas to prevent excessive chip stresses. Therefore, it is an object of the present invention to provide a highly reliable thermal chip structure and process for fabricating such a structure which eliminates hot spots across the chip area. A further object of the present invention is to provide a thermal structure and process for maintaining a more uniform chip temperature across the chip area.
SUMMARY OF THE INVENTION
To achieve the foregoing objects, the present invention is a heat sink or spreading assembly comprising a composite structure of the semiconductor chip layer, having both high and low power circuits formed in the chip with the high power circuits capable of generating “hot spots” during operation, and one or more thermal conductivity layers having a thermal conductivity substantially higher than the chip and a thickness greater than the chip layer. Preferably, the thickness of the high thermal conductivity layers, either individually or combined, are at least about two times thicker than the thickness of the semiconductor chip. The general process for fabricating the composite structure comprises: providing an integrated circuit semiconductor layer of a thickness “x” and containing high power circuits in certain areas of the chip capable of generating a highter temperature than the other circuits of the chip resulting in “hot spots” in these areas during operation of the chip; forming at least one thermal conductivity layer on the back of the semiconductor layer having a substantially higher thermal conductivity than the chip and preferably a thickness at least two times greater than “x” and with a thermal coefficient of expansion similar to the semiconductor chip; and providing heat conduction means to carry the heat away from the semiconductor chip composite, whereby during operation of the chip, the “hot spots” are dissipated and the maximum chip temperature is lowered to create a uniform and lower temperature across the chip. The preferred process for fabricating the composite structure comprises: forming on the backside of a semiconductor wafer, from which fabricated chips with both high and low power circuits will be diced, one or more high thermal conductive layers, removing any of deposited high conductive layers from the front side of the wafer and a sufficient amount of semiconductor material to thin the wafer to a thickness substantially less than the deposited thermal conductive layer. Alternatively, a wafer is fabricated with devices and diced into chips, some of which contain high power circuits capable of generating “hot spot” in the chip during operation. The chips containing such circuits are thinned on their back side and one or more thermal conductivity layers with a thermal conductivity layer substantially higher than the chip and a thickness substantially greater than the chip are bonded to the back side of the thinned chip.
More specifically relative to the preferred process, the semiconductor wafer comprises silicon (Si), gallium arsenide (Ga—As), or silicon germanium (Si—Ge) of a standard thickness on which is deposited a high thermal conductive layer of either &bgr;—SiC or diamond or a combination of both. After deposition, the front side of the wafer is lapped and polished to remove any deposited high conductive layer and to thin the semiconductor wafer so that the high conductive layer(s) are substantially thicker than the thinned wafer. devices are now fabricated in the front side of the wafer and contain circuits capable of creating “hot spots” and the wafer is diced into semiconductor chips. The semiconductor chips are mounted on a multilayer ceramic substrate. One or more ceramic substrates are mounted on multilayer printed circuit board to complete a package of highly integrated circuits. The chips mounted face up or front side up and wire bonded to the substrate but, preferably, to increase the chip input/output (I/O) density on the substrate, the semiconductor chips are mounted face down or front side down in a configuration known as flip chip. Area connections with controlled clapsed connected chips (C
4
) are used on the face of the chip which permits close spacing of the chips on the substrate. Although the flip chip mounting provides the advantage of increased chip I/O density, such mounting presents a more severe problem for dissipating the heat generated by the chips because the heat must be removed from the back of the chips.


REFERENCES:
patent: 4914551 (1990-04-01), Anschel et al.
patent: 5931222 (1999-08-01), Toy et al.
patent: 5952719 (1999-09-01), Robinson et al.
patent: 6104090 (2000-08-01), Unger et al.

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