Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-09-19
2004-05-18
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S111000, C438S121000
Reexamination Certificate
active
06737299
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor device packaging, and more particularly, to attaching a semiconductor die in a device package.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically fabricated on thin wafers of silicon. Several die are produced on each wafer, with each die representing a single semiconductor device. Each die on a wafer is tested for gross functionality, and sorted according to whether the die passes or fails the gross functionality test. After being sorted according to gross functionality, the wafers are cut using a wafer saw, and the individual die are singulated. The die determined to be non-functional are scrapped. The functional die are packaged and further tested to ensure that each packaged device satisfies a minimum level of performance. Typically, the functional devices are permanently packaged by encapsulating the die in a plastic package. Packaging of the functional devices facilitates handling of the devices and also protects the die from damage during the manufacture of circuits using the packaged devices.
There are several conventional structures and methods for packaging singulated die. For example, more common package types include small outline j-bend (SOJ) packages, thin small outline packages (TSOP), and zigzag in-line packages (ZIP). The finished packaged devices are often mounted onto a substrate to form a module. A singulated die is packaged in the aforementioned package types by attaching the die to a lead frame paddle and electrically coupling exposed bond pads of the die to metal leads. The lead frame, die, and a portion of the metal leads are subsequently encapsulated by a plastic resin to protect the integrated circuit from damage. The encapsulated device is then trimmed from the lead frame and the metal leads formed to the correct shape.
An alternative lead frame structure, known as lead on chip (LOC) may be employed instead of the structure having a lead frame paddle. In an LOC structure, individual metal leads are typically attached to the surface of the die using double-sided adhesive tape having a polyimide base coated on both sides with adhesive material. The metal leads and die are then heated to melt the adhesive material. The bond pads of the semiconductor die are subsequently wire bonded to a respective metal lead to electrically connect the semiconductor die to receive electrical signals applied to the conductive leads. The LOC lead frame and die are then encapsulated in a plastic resin, then followed by a trim and form process. The LOC structure and packaging process are described in U.S. Pat. No. 4,862,245 to Pashby et al., issued Aug. 29, 1989, and U.S. Pat. No. 4,916,519 to Ward, issued Apr. 10, 1990, which are incorporated herein by reference.
Recently, semiconductor manufacturers have developed a package structure where unpackaged die are mounted directly onto a substrate, for example, a printed circuit board, thus allowing modules to be designed with increased device density. The devices are mounted onto the substrate and are electrically coupled by wire bonding the bond pads of the die to conductive traces formed on the surface of the substrate. The die are typically attached to the substrate by using strips of single or double-sided adhesive tape that are sandwiched between the substrate and the die. Following attachment, the substrate and die are heated to cure the adhesive in order to firmly fix the die.
As described above, many of the current methods of packaging semiconductor die involve attaching the die to a lead frame or a substrate using a single or double-sided adhesive tape. However, a problem with the conventional die attachment structures is that they do not facilitate the transmission or dissipation of heat generated by the device while in operation. The heat generated by an integrated circuit fabricated on the semiconductor die may adversely affect the performance of the device if not dissipated. The problems associated with the heat generated by the individual devices have been precipitated by the demand for high speed memory systems.
Consequently, the individual devices generate more heat than when operated at slower speeds. For example, in a RAMBUS memory architecture, or other high-speed memory application, the heat generated by the individual packaged devices may operate at temperatures as high as 100° C. In the case where the generated heat is not dissipated, the temperature may be great enough to cause memory system errors. Therefore, there is a need for a means to dissipate excessive heat generated by an integrated circuit in a packaged semiconductor device when being operated.
SUMMARY OF THE INVENTION
The present invention is directed to a thermally conductive adhesive tape and method for its use in packaging integrated circuits fabricated on semiconductor material. The thermally conductive adhesive tape includes a thermally conductive base upon which an adhesive layer is laminated or coated onto at least one side of the thermally conductive base. Thermal energy may be dissipated by transferring the heat through the thermally conductive adhesive tape from the integrated circuit to the medium to which the integrated circuit is attached.
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paten
Dorsey & Whitney LLP
Everhart Caridad
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