Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2001-11-02
2003-03-18
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S678000, C257S679000
Reexamination Certificate
active
06534857
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices and more particularly to a high frequency field effect transistor power cell consisting of a plurality of same type of field effect transistor devices fabricated side-by-side and connected in parallel on a common semiconductor chip.
2. Description of Related Art
Field effect transistor (FET) devices are well known in the art. A typical FET device is shown in FIG.
1
and consists of a semi-insulating substrate
10
, an undoped buffer layer
12
, and an upper layer
14
which is doped with a semiconductivity type dopant, typically n-type semiconductor material. The doped upper layer
14
forms an active region which implements a current channel between source and drain contact regions
16
and
18
on which is formed source and drain connection terminals or electrodes
20
and
22
. The source and drain regions
16
and
18
are separated from one another by a space
23
including a gate electrode
24
which is formed on the surface
26
of the active layer
14
. The gate
24
acts to modulate the current in the channel beneath it as current traverses between the source and drain electrodes
20
and
22
.
The dimension of the gate
24
parallel to the current flow shown by the arrow
28
in
FIG. 1
is called the “gate length” and comprises the most critical dimension for the determination of high frequency response. The gate dimension into the paper and as shown in
FIG. 2A
, is called the “gate width” and determines the power of the device because total current flow is proportional to the gate width. Typical dimensions for the gate length are 0.25 to 0.75 microns (10
−6
m), while the gate width is loosely limited to something less than 100 to 400 microns, depending upon the particular design.
High power levels are typically obtained by forming a cell
30
of multiple FET devices in parallel on a common semiconductor chip
26
, such as silicon carbide (SiC), as shown in
FIGS. 2A and 2B
. There, reference numeral
28
denotes a metal flange on which the chip
26
is mounted. As shown in
FIG. 2A
, the combination of a plurality of parallel gate-source-drain structures having equal width gates
24
1
. . .
24
n
is referred to as a cell, as indicated by reference numeral
30
. The width of the cell
30
is the width of each individual gate
24
1
. . .
24
n
while the length of the cell is the number of gates times the “pitch” which is the distance
32
between neighboring gates such as gates
24
1
and
24
2
.
The cell
30
generates waste heat from each of the individual gate fingers
24
1
. . .
24
n
, which effectively becomes an area heat source in the overall cell. The waste heat from the cell area is mostly conducted downwardly through the chip to the metal flange, although the downward path is somewhat increased by the lateral spreading from the edges
34
and
36
in the longitudinal direction toward the end regions
38
and
40
(FIG.
5
).
The temperature rise due to waste heat adversely affects the transistor performance and reliability. Thermal design of the cell and transistor chip is therefore a critical part of the overall design of a high performance power FET device. The chip is typically thinned as much as possible in the width direction to minimize thermal impedance, while the area power density in the cell is controlled by limiting the finger-to-finger spacing or pitch. A small gate width, therefore, to the cell is preferably in order to maximize the level of spreading of the heat flow.
SUMMARY
Accordingly, it is an object of the present invention to provide an improvement in semiconductor devices.
It is another object of the invention to provide an improvement in power transistors.
And it is a further object of the present invention to provide an improvement in field effect power transistors.
And it is yet another object of the invention to provide thermal balance in a cell of field effect transistors residing on a common semiconductor chip.
These and other objects are achieved by a high power transistor structure comprised of a plurality of field effect transistors fabricated in parallel on a common semiconductor chip and wherein the gate electrodes of the field effect devices are in the form of parallel finger elements having a variable pitch between the fingers which decreases, such as uniformly or non-uniformly, from a central portion of the cell to opposite outer end portions thereof. The variable finger pitch results in a much more uniform temperature distribution with a lower peak temperature. Such an implementation of gate fingers operates to improve reliability as well as eliminating the fighting between fingers due to temperature-driven gain and phase variances.
Further scope of applicability of the present invention will become apparent from the detailed description provided hereinafter. It should be understood, however, that the detailed description and specific example, while disclosing the preferred embodiment of the invention, it is provided by way of illustration only inasmuch as various changes and modifications coming within the spirit and scope of the invention will become apparent to those skilled in the art from the following detailed description.
REFERENCES:
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patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4991916 (1991-02-01), Deaver
patent: 5408128 (1995-04-01), Furnival
patent: 5585288 (1996-12-01), Davis et al.
patent: 5917204 (1999-06-01), Bhatnagar et al.
patent: 6078194 (2000-06-01), Lee
patent: 6078501 (2000-06-01), Catrambone et al.
patent: 6146926 (2000-11-01), Bhatnagar et al.
patent: 6204554 (2001-03-01), Ewer et al.
Birch & Stewart Kolasch & Birch, LLP
Lindsay Jr. Walter L.
Niebling John F.
Northrop Grumman Corporation
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