Thermal vias-provided cavity-down IC package structure

Details Thermal vias-provided cavity-down IC package structure Thermal vias-provided cavity-down IC package structure

1999-03-11

2001-01-16

Tolin, Gerald (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S705000, C361S706000, C361S707000, C361S708000, C361S717000, C361S718000, C361S713000, C361S719000, C257S706000, C257S713000

Reexamination Certificate

active

06175497

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87116231, filed Sep. 30, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a thermal vias-provided cavity-down IC package structure, and in particular to a super high-efficiency thermal vias-provided cavity-down IC package structure.
2. Description of the Related Art
In a module including at least one integrated circuit (IC), a large number of electrically conductive wires is required to form a complete circuit for signal and power source inputs/outputs. In the past, there were many different types of IC packages. The common packages are a planar package, a hermetic and plastic chip carrier package and a grid array package.
In conventional and widely used IC packages, a lead frame is used to electrically connect a semiconductor chip and the external leads of a package. Since ICs are becoming increasingly more precise and complicated, the number of wires required is greatly increased with the sizes of packages remaining the same or being reduced. Therefore, the conventional lead frame cannot meet practical requirements. To resolve this problem, a new type of IC package for containing a greater number of wires is urgently required to complete more complicated circuits.
Accordingly, a ball grid array (BGA) IC package used to contain a greater number of wires was introduced. In general, BGA is a square package where solder balls are used for external electrical connections instead of lead pins. The solder balls are used to electrically connect to a printed wire board, a printed circuit board or bonding pads of other ICs.
In practice, a conventional BGA substrate is a small, double-layer or multi-layer, printed circuit board. A chip is electrically connected to the BGA substrate through a plurality of wires. Moreover, electrical connections between conductive layers in the BGA substrate are completed via plated-through-holes or metal plugs.
FIG. 1
is a schematic, cross-sectional view illustrating a cavity-down BGA IC package structure which is disclosed in U.S. Pat. No. 5,357,672 issued to LSI Logic Corporation. As shown in
FIG. 1
, three layers of printed wire boards
100
,
102
and
104
are attached to each other through prepregs
106
,
108
and
110
with a cavity
111
formed therein. A chip
112
is disposed at the center of the cavity, and is surrounded by trapezoidal edges of the 3-layer printed wire board. The trapezoidal edges are designed with bonding pads
114
and
116
thereon. Bonding pads
118
surrounding the chip
112
are electrically connected to the bonding pads
114
and
116
through bonding wires
120
, and then to bumps
124
through plated through hole
122
for a signal transmission with a main board (not shown). A heat sink
130
is disposed on the back of the chip
112
for heat transfer.
In this patent, the three layers of printed wire boards
100
,
102
and
104
attached to each other through prepregs
106
,
108
and
110
serve as a substrate, and the cavity
111
formed in the substrate is chiefly used to contain the chip
112
. Therefore, the bumps
124
can be formed on the same side as the chip
112
. Compared to a general BGA IC package with a chip and bumps formed on two opposite sides, two conductive layers are saved.
In a conventional cavity-down BGA, PGA (Pin Grid Array) or multi-chip module (MCM) IC package, at least two conductive layers, such as conductive layers
126
and
128
shown in
FIG. 1
, are formed in a multi-layer printed wire boards serving as a substrate, with a cavity formed in the multi-layer printed wire board. Since a general chip has a thickness approximately equal to or greater than that of the substrate and the chip and solder balls are located on the same side, the contact between the solder balls and a main board is hindered during bonding and molding. For this reason, in a conventional cavity-down IC package, a chip is generally ground to have a thickness ranging from 10 to 25 mil. However, wafers are easily broken during grinding, resulting in an expensive loss of material.
Furthermore, in the conventional cavity-down BGA, PGA or MCM IC package, only one planar heat sink, such as the one
130
shown in
FIG. 1
, is disposed on the back of a chip. However, this heat sink design cannot meet requirements for highly integrated, high-speed ICs where a great amount of heat is generated, and all devices formed in the ICs are extremely sensitive to temperature.
SUMMARY OF THE INVENTION
In view of the above, an object of the invention is to provide a thermal vias-provided cavity-down IC package structure where a chip mount pad is directly attached to a heat sink made of metal, thermally conductive ceramics or polymer through a silver paste, thereby forming a most direct and short thermally conductive path to a carried chip. Thus, part of heat energy can be further transferred from thermal vias distributed close to the heat sink by plated-through-holes, bonding pads and solder balls of a substrate to a motherboard on which the substrate is mounted, thereby enhancing heat transfer efficiency.
Another object of the invention is to provide a thermal vias-provided cavity-down IC package structure in which a heat sink is designed as a concave shape in coordination with thicknesses of a chip and a substrate for easy bonding and molding. In addition, the structure is also suitable for conventional BGA, PGA, CSP (Chip Scale Package) and MCM IC packages.
The thermal vias-provided cavity-down IC package structure of the invention includes a substrate, a heat sink and an adhesive layer for attaching the substrate and the heat sink. The substrate is formed of multiple layers of printed circuit boards which are attached to each other, and have a cavity formed at the center thereof. A plurality of thermal vias is formed surrounding the substrate. The head sink is divided into a chip mount area and a thermal via joint area. The chip mount area is used for a chip mount pad to be disposed thereon, wherein a chip is connected to the heat sink through the chip mount pad. The thermal via area is electrically coupled to the thermal vias thereby to form an approximate short path or a short path. Thus, heat energy is transferred not only by the heat sink directly, but also from the heat sink to the substrate through the thermal vias.


REFERENCES:
patent: 5097318 (1992-03-01), Tanaka et al.
patent: 5404273 (1995-04-01), Akagawa
patent: 5409865 (1995-04-01), Karnezos
patent: 5646373 (1997-07-01), Collins et al.
patent: 5652463 (1997-07-01), Weber et al.
patent: 5675404 (1997-10-01), Nagase et al.
patent: 5724232 (1998-03-01), Bhatt et al.
patent: 5814883 (1998-09-01), Sawai et al.
patent: 5831825 (1998-11-01), Fromont
patent: 5905634 (1999-05-01), Takeda et al.
patent: 5959356 (1999-09-01), Oh
patent: 5990550 (1999-11-01), Umezawa
patent: 6008536 (1999-12-01), Mertol

Affiliated with

Also associated with

Rating

Thermal vias-provided cavity-down IC package structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Thermal vias-provided cavity-down IC package structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thermal vias-provided cavity-down IC package structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2480387