Thermal stress resistant semiconductor device mounting arrangeme

Details Thermal stress resistant semiconductor device mounting arrangeme Thermal stress resistant semiconductor device mounting arrangeme

1992-04-23

1994-12-20

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257724, 361760, H01L 2302

Patent

active

053748484

ABSTRACT:
Cracks in solder connecting terminal leads of an IC to a circuit board are prevented by reducing the stress due to the difference in the coefficients of thermal expansion of a pair of IC packages mounted on opposite surfaces of a circuit board and the circuit board. In this invention, the position of an IC package mounted on the upper surface of a circuit board is spaced from the position of an IC package mounted on the lower surface of the circuit board. Alternatively, the IC packages are mounted on the upper and lower surfaces in directions which are substantially orthogonal. Alternatively, the IC packages are mounted such that the positions of lead portions of one of the upper IC packages are spaced from the positions of the lead portions of the other IC package by a distance which is at least 2.4 times the thickness of the circuit board.

REFERENCES:
patent: 4984064 (1991-01-01), Toshio et al.
patent: 5055912 (1991-10-01), Murasawa et al.

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