Thermal neutron shielded integrated circuits

Details Thermal neutron shielded integrated circuits Thermal neutron shielded integrated circuits

1995-04-03

2001-05-29

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S660000

Reexamination Certificate

active

06239479

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to semiconductor devices and circuits, and, more particularly, to both semiconductor device packaging and system level containers.
Many digital semiconductor devices, such as DRAMs, SRAMs, A/D converters, and so forth rely on electrical charge on a capacitive node for storage of a digital signal, and thus such devices are sensitive to events which transport unintended charge to the node. For example, silicon devices in airplanes encounter cosmic rays which include high energy (1-10 Mev) neutrons;
FIG. 1
shows the high energy neutron flux as a function of altitude. Such high energy neutrons may react with silicon nuclei in an integrated circuit substrate to yield heavy recoil nuclei which generate bursts of electrical charge that can migrate to a node in the substrate and upset a stored charge. Gossett et al, Single Event Phenomena in Atmospheric Neutron Environments, 40 IEEE Tr.Nuc.Sci. 1845 (1993), analyze upset in a bipolar SRAM.
At sea level cosmic rays include some high energy neutrons, but generally neutrons moving through the atmosphere thermalize (primarily scatter from nitrogen and oxygen nuclei) and their energies tend towards kT (0.025 eV at room tempeature).
FIG. 2
heuristically illustrates the sea level neutron flux as a function of energy. See Hess et al, Cosmic-Ray Neutron Energy Spectrum, 116 Phys.Rev. 445 (1959); Ziegler et al, The Effect of Sea Level Cosmic Rays on Electronic Devices, 52 J.Appl.Phys. 4305 (1981); and Nakamura et al, Altitude Variation of Cosmic-Ray Neutrons, 53 Health Phys. 509 (1987). As the neutrons with energies well above kT pass through matter, they continue thermalizing and thus the source of thermal neutrons may be considered continuous.
One approach to compensate for such cosmic ray hazards simply increases node capacitances to require a large unintended charge for upset. However, this increases the substrate area used by a circuit and thus increases costs.
Semiconductor device packages typically fall into one of two types: plastic encapsulation and ceramic packages. Plastic encapsulation surrounds a semiconductor die plus its bond wires and lead frame with a roughly 2 mm thick plastic coating made of typically 27% novalac epoxy, 70% inert filler, 2% flame retardant, 1% colorant, plus accelerator, curing agent, and mold-release agent. The filler may be powdered quartz. However, quartz typically has natural uranium and thorium impurities. U and Th radioactive decay gives rise to alpha particles which generate bursts of electrical charges analogous to silicon nucleus recoil products arising from high energy neutron reaction. These likewise can migrate and upset stored signal charge on a node. Early approaches to controlling such alpha particle generated upsets placed an alpha particle absorbing barrier, such as a 30 &mgr;m thick silicone rubber layer, between the die and the surrounding plastic. An alpha particle loses energy as it passes through matter, and typical ranges are 5-100 &mgr;m for 1-10 MeV alphas in various density materials with higher density yielding shorter ranges. Thus the 30 &mgr;m of silicone rubber barrier would dissipate most of a typical alpha particle energy prior to the alpha entering the active device areas of an integrated circuit.
Subsequently, fillers using quartz with low impurity levels brought the radiation down to less than 0.001 alpha/cm
2
/hour and thus effectively eliminated the problem and the need for the barrier.
Ceramic packages typically have a body of 90% alumina plus 10% glass with lids of gold-plated kovar, a glass sealer, and air within the package cavity. All of these components may have alpha-emitting radioactive impurities, for example radon in cavity air. These components, particularly the aluminum and gold, may be purified to limit radioactive isotope levels and avoid excessive alpha generated upsets.
SUMMARY OF THE INVENTION
The present invention provides a thermal neutron absorbing layer both within integrated circuit packaging at the die level and also at the circuit board container level. Preferred embodiment thermal neutron absorbing layers include compounds of isotopes with anomolously large absorption cross sections such as of
157
Gd,
149
Sm,
113
Cd, and
10
B.
This thermal neutron absorbing layer has the advantage of decreasing upset sensitivity in devices caused by cosmic ray generated thermal neutrons which may react with the materials making up a device and generate secondary radiation that leads to upsets. The thermal neutron absorbing layer may be used in addition increased node capacitance sensitivity suppressors or alone. And use of an absorbing layer at the circuit board container level permits use of integrated circuit packages without any special precautions.


REFERENCES:
patent: 3611207 (1971-10-01), Klahr
patent: 4415526 (1983-11-01), Garrett
patent: 4691243 (1987-09-01), Canella et al.
patent: 5391924 (1995-02-01), Uchida et al.
patent: 55-088358 (1980-07-01), None
patent: 1028952 (1989-01-01), None
patent: 5267504 (1993-10-01), None
Enhanced Adhesion and Thermal Conductivity of Epoxy Sealant, IBM TDB vol. 28 No. 11 4/86 p. 4710.

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