Thermal head driving integrated circuit

Details Thermal head driving integrated circuit Thermal head driving integrated circuit

1999-10-28

2002-03-19

Le, N. (Department: 2861)

Incremental printing of symbolic information

Thermal marking apparatus or processes

Having driving circuitry for recording means

Reexamination Certificate

active

06359639

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is related to a thermal head driving integrated circuit (IC) for entering thereinto a data signal to control energizing of a heating resistive element.
Referring now to
FIG. 11
, an example of a conventional thermal head driving IC will be briefly explained. Such a thermal head driving integrated circuit is disclosed in, for instance, Japanese Patent Application Laid-Open No. Hei 3-53950. As shown in this drawing, the thermal head driving IC
0
controls energizing of a plurality of heating resistive elements
1
, and is equipped with the output terminals DO
1
to DO
64
connected to the respective heating resistive elements
1
. As a result, in this example, the thermal head driving IC
0
can drive 64 of these heating resistive elements 1 at a time. One terminal of the respective heating resistive elements
1
are commonly connected to each other, to which the energizing power supply voltage (for example, 24 V) is applied. The other terminal of the respective hearing resistive elements
1
are connected via the output terminals to drive transistors
2
. The drive transistors
2
constitute a driver, and are composed of the N-channel type MOS transistors, in this example. Each of the drive transistors
2
is an open drain output, and all of the sources of these drive transistors
2
are connected to a ground potential VSS. The output terminal of an AND gate circuit
3
is connected to the gate of each drive transistor
2
.
Reference numeral
4
shows a shift register for sequentially storing thereinto 1-line data, and is arranged with a series-connection of D-FFs. The shift register
4
is connected via a buffer
8
to a data input terminal SI. Also, the final stage of the shift register
4
is connected via the buffer
8
to a data output terminal SO. In addition, a clock signal is supplied from a control terminal CLK via the buffer
8
to the D-FFs of the respective stages of the shift register
4
.
Reference numeral
5
shows a latch circuit for latching the data of the shift register
4
in a batch mode. A latch signal is supplied from a control terminal LCH via the buffer
8
. The outputs of the respective stages of the latch circuit
5
are connected to one input terminal of the corresponding AND gate circuit
3
. The other input terminals of the respective AND gate circuits
3
are commonly connected to the output terminal of an inverter
7
. A strobe signal is applied via a control terminal STB to the input terminal of the inverter
7
. It should be noted that the power supply voltage VDD is applied to this thermal head driving IC
0
. The input terminal of the inverter
7
is connected via the pull-up resistor to the VDD.
The shift register
4
reads the data signal inputted into the data input terminal SI at the rising edge of the clock signal applied to the control terminal CLK. When the control terminal LCH is at the L-level, the latch circuit
5
latches the data stored in the respective stages of the shift register
4
in the batch mode. When the control terminal LCH is at the H-level, this latch circuit
5
holds the data latched immediately before this control terminal LCH becomes the H level. The data latched in the latch circuit
5
is outputted via the AND gate circuit
3
to the corresponding drive transistor
2
when the control terminal STB is at the L-level.
In other words, when the control terminal STB is at the L-level and the data outputted from the latch circuit
5
is at the H-level, the drive transistor
2
is turned ON, and thus, the corresponding heating resistive element
1
is energized. Conversely, when the control terminal STB is at the L-level and the data is at the L-level, the drive transistor
2
is turned OFF.
When the control terminal STB is set to the H-level, all of the drive transistors
2
are turned OFF irrespective of the output of the latch circuit
5
.
SUMMARY OF THE INVENTION
For example, when a print operation is carried out on a sheet of paper having a size of A4 in a line sequential manner, 1,728 of the heating resistive elements
1
are arranged in one column. To drive these 1,728 dots of heating resistive elements, 27 of the thermal head driving ICs
0
having 64 driver output terminals need be mounted in one column on a circuit board. In order to reduce the total number of these thermal head driving IC approximately ½, for example, as represented in
FIG. 3
, such a thermal head driving IC
0
has been developed, in which two stages of shift registers
41
and
42
are built in a series manner. Each of the shift registers
41
and
42
has 64 output stages. As an entire circuit, this IC
0
has 64 2=128 driver output terminals. As a result, the total number of the packaged ICs can be reduced by ½, as compared with that of the ICs indicated in FIG.
11
. The front-staged shift register
41
is provided with the data input terminal SI
1
and the data output terminal SO
1
, and also, the rear-staged shift register
2
is equipped with the data input terminal SI
2
and the data output terminal SO
2
.
As a consequence, the operation of the IC itself is similar to that of the IC shown in the drawing. Since both the shift registers
41
and
42
are used in a parallel manner, one set of 64 pieces of data can be written into the respective shift registers
41
and
42
at the same time.
On the other hand, in the IC shown in
FIG. 3
, when specifically no highspeed printing operation is required, the output terminal SO
1
of the front-staged shift register
41
and the input terminal SI
2
of the rear-staged shift register
42
are commonly connected to each other by way of a wire bonding and the like, so that both the shift registers
41
and
42
may be used in the series manner. In this case, while the data are entered from the terminal SI
1
, 128 pieces of such data are sequentially written into the series-connection between the shift register
41
and the shift register
42
. In this manner, the total number of input data (namely, the number of input lines of data) with respect to the ICs arranged in one column can be reduced by ½. However, since the intermediate input/output terminals SO
1
and SI
2
must be connected by way of the wire bonding, there is a demerit in view of cost. Also, since the stray capacitance C
p
is produced at the wire bonding portion, it could not avoid such a problem that the data transfer speed between the shift registers
41
and
42
is lowered.
Thus, it is conceivable that a switch circuit is employed which may internally connect/disconnect both the output terminal SO
1
of the front-staged shift register
41
and the input terminal SI
2
of the rear-staged shift register
42
, so that both the shift registers
41
and
42
may be switched in the series use mode and the parallel use mode while preventing an occurrence of a stray capacitance.
In such a case that the series use mode and the parallel use mode are switched by employing such a switch circuit, when the output terminal SO
1
and the input terminal SI
2
are provided, the total number of input/output pads is increased, so that an IC chip will become bulky and also the total number of bondings will be increased.
However, in the case that both the shift registers
41
and
42
are connected so as to be used in the series manner, both the output terminal SO
1
of the front-staged shift register
41
and the input terminal SI
2
of the rear-staged shift register
41
and the input terminal SI
2
of the rear-staged shift register
42
are used. Also, in the case that both the shift registers
41
and
42
are disconnected from each other so as to be used in the parallel manner, although the input terminal SI
2
of the rear-staged shift register
42
is used, the output terminal SO
1
of the front-stage shift register
41
is not always used. There is another case that tests are separately carried out as to whether or not both the shift registers
41
and
42
are operated under normal condition. In this case, the output terminal SO
1
of the shift register
41

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