Thermal gradient control of high aspect ratio etching and...

Details Thermal gradient control of high aspect ratio etching and... Thermal gradient control of high aspect ratio etching and...

2011-08-30

2011-08-30

Norton, Nadine (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S701000, C438S978000, C438S719000, C438S723000, C438S735000, C438S743000, C216S067000, C216S079000, C216S080000

Reexamination Certificate

active

08008209

ABSTRACT:
A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.

REFERENCES:
patent: 4684436 (1987-08-01), Burns et al.
patent: 6740194 (2004-05-01), Rushford et al.
patent: 6903031 (2005-06-01), Karim et al.
patent: 6936182 (2005-08-01), Rushford
patent: 2005/0118826 (2005-06-01), Boyd et al.

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