Thermal bus design to cool a microelectronic die

Details Thermal bus design to cool a microelectronic die Thermal bus design to cool a microelectronic die

2001-08-17

2003-02-11

Chervinsky, Boris (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S707000, C361S710000, C361S720000, C257S706000, C257S717000, C174S016300, C165S080200, C165S080300, C165S185000

Reexamination Certificate

active

06519154

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of heat transfer and, in particular, the present invention relates to thermal management of microelectronic electronic devices.
BACKGROUND
In one embodiment, the present invention is used to transfer heat generated by electronic devices or groups of devices, such as transistors, as are commonly included on integrated circuit (IC) chips. A brief discussion of some electronic systems using IC's, such as personal computers or lower level computer components, is included below to show some possible areas of application for the present invention.
IC's are typically formed on microelectronic dies and assembled into microelectronic packages by physically and electrically coupling them to a package substrate made of organic or ceramic material. One or more microelectronic packages can be physically and electrically coupled to a printed circuit board (PCB) to form an “electronic assembly”. The “electronic assembly” can be part of an “electronic system”. An “electronic system” is broadly defined herein as any product comprising an “electronic assembly”. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
An IC is fabricated on a microelectronic die that may comprise a number of metal layers selectively patterned to provide metal interconnect lines (referred to herein as “traces”), and one or more electronic devices attached in or on one or more surfaces of the microelectronic die. The electronic device or devices are functionally connected to other elements of an electronic system through a hierarchy of electrically conductive paths that include the metal traces. The traces typically carry signals that are transmitted between the electronic devices, such as transistors, of the IC. Electronic devices and traces can be configured in an IC to form processors.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding forming electronic devices such as transistors in IC's, where each new generation of IC must provide increased performance, particularly in terms of an increased number of devices and higher clock frequencies, while generally being smaller or more compact in size. As the density and clock frequency of IC's increase, they accordingly generate a greater amount of heat. However, the performance and reliability of IC's are known to diminish as the temperature to which they are subjected increases, so it becomes increasingly important to adequately dissipate heat from IC environments.
Additionally, specific areas of a die on which an IC is formed are often more frequently used than other areas of the die. For example, a floating point unit (FPU) area will typically generate a higher amount of heat than other areas on the die. These areas lead to “hot spots” on the die that significantly increase the local temperature surrounding these hot spots, and also elevate the overall average temperature of the die.
FIG. 1
illustrates a cross-sectional representation of a common configuration microelectronic package
30
. Microelectronic package
30
represents a typical structure that includes a microelectronic die
40
mounted in “flip-chip” orientation with its active side
44
facing downward to couple with electrical contacts or lands on the package substrate
50
. Solder balls or bumps
42
make the electrical connection with the contacts on the package substrate, while an underfill material
52
maintains a mechanical bond between the microelectronic die
40
and the package substrate
50
. The package substrate
50
can include additional lands
54
and solder balls
56
on its opposite surface for mating with additional packaging structure (not shown).
Die
40
generates its heat from internal structure, including wiring traces, that is located near its active side
44
. However, a significant portion of the heat is dissipated through its back side
46
. Heat that is concentrated within the die is dissipated to a large surface that is in contact with the die in the form of a thermally conductive package cover
60
. To improve the thermal conductivity between the die and the package, cover
60
, a first thermal interface material (TIM)
70
is often provided between the die and package cover
60
. To further dissipate heat from the package cover
60
, a heat sink
80
optionally having heat fins
82
is often coupled to the package cover
60
. Heat sink
80
dissipates heat into the ambient environment. A second layer of TIM
75
may be included between the package cover
60
and the heat sink
80
to further facilitate the conduction of heat to the heat sink
80
and out to ambient. Arrows
84
show the conduction of heat from the microelectronic die
40
out to the heat sink
80
, where the heat is transmitted to ambient.
FIG. 2
schematically shows the resistance to the flow of heat generated in the microelectronic package from FIG.
1
. The resistor symbols represent the thermal resistance through the thickness of each material noted. The shaded circles represent the interfaces between the various materials. In this schematic, heat is conducted from a heat generating electronic device, such as a transistor junction, through the microelectronic die
40
to the backside
46
of the die, through the first TIM
70
, and into the package cover
60
.
A device
210
is schematically located on the active side
44
of the microelectronic die
40
. The die resistance
220
is shown from the device
210
, to the backside
46
of the microelectronic die
40
. The die/TIM interface
230
is between the backside
46
of the die and the first TIM
70
. The first TIM resistance
240
is shown from the die/TIM interface
230
to the package cover
60
, which defines a TIM/cover interface
250
.
For ease of discussion, any conducting member resistance or thermal resistance associated with the interfaces is included in the bulk resistance values. The calculation for total thermal resistance of a single conduction path with multiple materials in series is defined as:
R
tot
=R
1
+R
2
. . . +R
n
  Equation 1:
where R
1
to R
n
represent the thermal resistance values of the individual materials. A typical thermal resistance value for bulk silicon is 2.5 C/W and a typical value for a first TIM is 0.5 C/W. A typical total thermal resistance (R
tot
) for the system in
FIG. 2
would therefore be 2.5 C/W+0.5 C/W=3.0 C/W.
With the advent of high performance IC's and their associated packages, electronic devices have required more innovative thermal management to, dissipate heat. Increasing speed and power in processors, for example, generally carry with it a “cost” of increased heat in the microelectronic die that must be dissipated. What is needed is a device and method to more effectively cool microelectronic dies containing IC's such as processors. What is also needed is a device and method that can specifically cool local hot spots on a microelectronic die.


REFERENCES:
patent: 5866943 (1999-02-01), Mertol
patent: 6008536 (1999-12-01), Mertol
patent: 6014314 (2000-01-01), Mikubo
patent: 6184580 (2001-02-01), Lin
patent: 6188578 (2001-02-01), Lin et al.
patent: 6229702 (2001-05-01), Tao et al.
patent: 6246583 (2001-06-01), Cronin et al.
patent: 6351194 (2002-02-01), Takahashi et al.

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