Thermal annealing process for producing silicon wafers with...

Details Thermal annealing process for producing silicon wafers with... Thermal annealing process for producing silicon wafers with...

2002-03-29

2004-06-01

Stein, Stephen (Department: 1775)

Stock material or miscellaneous articles

Circular sheet or circular blank

C428S446000, C117S003000, C117S928000, C423S348000

Reexamination Certificate

active

06743495

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a process for thermally treating or annealing a silicon wafer to reduce the concentration of agglomerated vacancy defects without substantially increasing the appearance of haze on the surface of the thermally treated silicon wafer.
Single crystal silicon wafers are commonly manufactured by a process which starts with the growth of a monocrystalline silicon ingot produced by the Czochralski (“Cz”) method or the float-zone (FZ) method. The crystal ingot is typically sliced into wafers with a wire-saw, the wafers are flattened by lapping and chemically etched to remove mechanical damage and contamination. After being etched, the wafers are polished on one or both sides.
A polished wafer typically has undesirable defects (e.g., Crystal Originated Pits/Particles (COPs)) on the surface that were formed as the ingot cooled after solidification which are detectable by laser scatter inspection tools. Such defects arise, in part, due to the presence of an excess (i.e. a concentration above the solubility limit) of intrinsic point defects, which are known as vacancies and self-interstitials. Silicon crystals grown from a melt are typically grown with an excess of one or the other type of intrinsic point defect, either crystal lattice vacancies or silicon self-interstitials. It has been suggested that the type and initial concentration of these point defects in the silicon are determined at the time of solidification and, if these concentrations reach a level of critical supersaturation in the system and the mobility of the point defects is sufficiently high, a reaction, or an agglomeration event, will likely occur. Agglomerated intrinsic point defects in silicon can severely impact the yield potential of the material in the production of complex and highly integrated circuits. Examples of vacancy-type intrinsic point defects (hereinafter “agglomerated vacancy defects”) include dislocations, surface defects, Flow Pattern Defects (FPDs), COPs, and oxidation induced stacking faults (OISF).
To date, there generally exists three main approaches to dealing with the problem of agglomerated intrinsic point defects. The first approach includes methods which focus on crystal pulling techniques in order to reduce the number density of agglomerated intrinsic point defects in the ingot. For example, it has been suggested that the number density of agglomerated defects can be reduced by (i) controlling v/Go to grow a crystal in which crystal lattice vacancies are the dominant intrinsic point defect, and (ii) influencing the nucleation rate of the agglomerated defects by altering (generally, by slowing down) the cooling rate of the silicon ingot from about 1100° C. to about 1050° C. during the crystal pulling process. While this approach reduces the number density of agglomerated defects, it does not prevent their formation and reducing the cooling rate decreases the throughput of the crystal growth apparatus thereby increasing the cost of producing wafers.
A second approach to dealing with the problem of agglomerated vacancy defects is the epitaxial deposition of a thin crystalline layer of silicon on the surface of a single crystal silicon wafer. This process provides a single crystal silicon wafer having a surface which is substantially free of agglomerated vacancy defects; however, the cost of the wafer substantially increases.
The third approach to dealing with the problem of agglomerated vacancy defects includes methods which focus on the dissolution or annihilation of the vacancy defects subsequent to their formation. Generally, this is achieved by using high temperature heat treatments of silicon wafers. The reduction of COPs is of particular interest because Gate Oxide Integrity failures correlate to the concentration of COPs on the wafer surface. D. Graf, M. Suhren, U. Schmilke, A. Ehlert, W. v. Ammon and P. Wagner.,
J. Electrochem. Soc.
1998, 145, 275; M. Tamatsuka, T. Sasaki, K. Hagimoto and G. A. Rozgonyi, Proc. 6th. Int. Symp. On Ultralarge Scale Integration Science and Technology “ULSI Science and Technology/1997,
” The Electrochemical Society
1997, PV97-3, p. 183; and T. Abe,
Electrochem. Soc. Proc.
1998, PV98-1, 157; N. Adachi, T. Hisatomi, M. Sano, H. Tsuya,
J. Electrochem. Soc.
2000, 147, 350. COPs within an ingot or wafer are octahedral voids. At the surface of a wafer, the COPs appear as pits with silicon dioxide covered walls and are typically about 50-300 nm wide and can be up to about 300 nm deep. It is presently believed that heat treating a wafer in certain ambients increases the migration of silicon atoms to the COPs which decreases the depth of the COPs until they appear as shallow dish-like depressions that are not usually detected by automated inspection tools.
Previously disclosed heat treatments, or thermal annealing processes, include long term annealing in a hydrogen atmosphere (e.g., longer than about 30 minutes) which produces virtually COP-free surfaces, however, the duration is cost prohibitive. D. Graf, U. Lambert M. Brohl, A. Ehlert, R. Wahlich, P. Wagner.,
J. Electrochem. Soc.
1995, 142, 3189. Short term hydrogen annealing processes (less than about 5 minutes) do not sufficiently annihilate COPs. A significant drawback to annealing a silicon wafer in a hydrogen ambient (short or long term) is the significant increase in haze on the wafer surface (e.g., to levels greater than about 1.2 ppm measured by a SURFSCAN 6220 laser scatter inspection tool or to levels greater than about 0.2 ppm measured by a SURESCAN SP1 laser scatter inspection tool which are available from KLA-Tencor of San Jose, Calif., U.S.A.). Annealing a wafer in an argon ambient has also been disclosed. D. Graf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon and P. Wagner,
Electrochem. Soc. Proc.
1996, 96-13, 117; Iida, W. Kusaki, M. Tamatsura, E. Iino, M. Kimura and S. Murasoka,
Electrochem. Soc. Proc.
1999, 99-1, 449. Although annealing in argon annihilates COPs at the surface and near-surface (e.g., extending inward from the surface about 5000 nm) of the wafer more effectively than an H
2
ambient, it results in considerably higher haze levels than that of H
2
annealing. Short high temperature annealing cycles (less than about 5 minutes) in a mixture of H
2
and Ar have also been attempted for surface COP annihilation and GOI improvement with similar increases in the haze. T. Abe,
Electrochem. Soc. Proc.
1998, 98-1, 157; M. Tamatsuka, N. Kobayashi, S. Tobe, and T. Masiu,
Electrochem. Soc Proc,
1999, 99-1, 456); D. Gräf, M. Suhren, U. Lambert, R. Schmolke, A. Ehlert, W. v. Ammon, and P. Wagner,
Electrochem. Soc. Proc.
1996, 96-13, 117; and W. Iida, M. Kusaki, E. Tamatsura, M. K. Iino S. Muraoka,
Electrochem. Soc. Proc.
1999, 99-1, 449.
In view of these shortcomings, a need continues to exist for a low-cost method to annihilate or reduce the size of silicon wafer surface and/or sub-surface defects without the formation of excessive haze.
SUMMARY OF THE INVENTION
Among the objects of the present invention, therefore, is the provision of a low-cost process for the manufacture of silicon wafers to reduce the size of silicon wafer surface and/or sub-surface defects without the formation of excessive haze.
Briefly, therefore, the present invention is directed to a process for manufacturing a silicon wafer sliced from a single crystal ingot, the silicon wafer having a front surface, a back surface, an imaginary central plane between the front and back surfaces, and exposed agglomerated vacancy defects on the front surface, the process comprising:
a. cleaning the front surface of the silicon wafer at a temperature of at least about 1100° C. by exposing the front surface to a cleaning ambient comprising H
2
, HF gas, or HCl gas to remove silicon oxide from the front surface; and
b. exposing the cleaned front su

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