Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1999-04-23
2001-10-02
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C349S043000, C349S139000
Reexamination Certificate
active
06297519
ABSTRACT:
This application is based on Japanese patent applications HEI 10-243449 filed on Aug. 28, 1998 and HEI 11-22501 filed on Jan. 29, 1999, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. a) Field of the Invention
The present invention relates to an indium tin oxide (ITO) film contact structure, a thin film transistor (TFT) substrate, and its manufacture, and more particularly to a structure for electrically contacting an ITO film with an Al alloy film, a TFT substrate having such a contact structure, a method of manufacturing such a TFT substrate, and a TFT substrate with external connection terminals.
2. b) Description of the Related Art
FIG. 8
is a cross sectional view of a TFT and a pixel electrode of a conventional active matrix type liquid crystal display panel. TFT's are disposed in a matrix pattern on an image display area of a glass substrate
1
, and external terminals
3
are disposed in a border area around the image display area.
FIG. 8
shows a single TFT
10
among a plurality of TFT's . TFT
10
is constituted of a gate electrode
11
, a channel layer
12
, a channel protective film
18
, a source electrode
13
S, and a drain electrode
13
D. The gate electrode
11
is disposed on the surface of the glass substrate
1
. A first insulating film
4
is formed on the glass substrate
1
, covering the gate electrode
11
, and the channel layer
12
is formed on the first insulating film
4
, overriding the gate electrode
11
. The channel protective film
18
protects a surface of the channel layer
12
over the gate electrode
11
.
Partial surfaces of the channel layer
12
on both sides of the gate electrode
11
are covered with the source electrode
13
S and drain electrode
13
D. Each of the source electrode
13
S and drain electrode
13
D has a four-layer structure having an amorphous silicon film
14
, a lower Ti film
15
, an Al film
16
, and an upper Ti film
17
laminated in this order from the bottom.
A second insulating film
30
is formed on the first insulating film
4
, and covers TFT
10
. An opening
31
is formed through the second insulating film
30
in an area corresponding to the source electrode
13
S. An indium tin oxide (ITO) film
35
is formed on the inner surface of the opening
31
and on a partial surface of the second insulating film
30
. The ITO film
35
is connected to the source electrode
13
S at the bottom of the opening
31
.
In the border area, the external terminal
3
is covered with the first and second insulating films
4
and
30
. An opening
40
is formed through these two first and second insulating films
4
and
30
, the opening
40
exposing a partial top surface of the external terminal
3
.
The lower Ti film
15
inserted between the Al film
16
and amorphous silicon layer
14
prevents the element performance from being degraded by Al diffusion. If the Al film
16
is directly contacted with the ITO film
35
, a contact resistance is high. The upper Ti film
17
inserted between the Al film
16
and ITO film
35
lowers the contact resistance.
In the conventional active matrix type liquid crystal display panel shown in
FIG. 8
, the openings
31
and
40
are formed at the same time. The depth of the opening
31
corresponds to the thickness of the second insulating film
30
, whereas the depth of the opening
40
corresponds to a total thickness of the first and second insulating films
4
and
30
. Therefore, while the first insulating film
4
is etched to form the opening
40
, the upper Ti film
17
on the bottom of the opening
31
is exposed to the etching atmosphere. If the upper Ti film
17
on the bottom of the opening
31
is completely removed, the ITO film
35
directly contacts the Al film so that the contact resistance becomes high.
In order to leave the upper Ti film
17
on the bottom of the opening
31
with good reproductivity, it is necessary to make the upper Ti film
17
sufficiently thick. For example, it is preferable to make the upper Ti film
17
have a thickness of 100 nm or more. As the upper Ti film
17
is made thick, it takes a longer time to etch and pattern the source and drain electrodes
13
S and
13
D, so that improvement on productivity is hindered.
FIG. 9
is a cross sectional view of a terminal formed on the surface of a conventional TFT substrate. A gate insulating film
4
covers the surface of a glass substrate
1
. An amorphous silicon film
12
a
is formed on a partial surface area of the gate insulating film
4
. A terminal
21
a
is formed on the amorphous silicon film
12
a
. The terminal
2
la has a lamination structure of an amorphous silicon film
14
a
, a lower Ti film
15
a
, an Al film
16
a
, and an upper Ti film
17
a
, sequentially laminated in this order. In the pixel area, the amorphous silicon film
12
a
constitutes a channel layer of a TFT, and the four layers from the amorphous silicon film
14
a
to the upper Ti film
17
a
constitute a source electrode, a drain electrode, and a drain bus line, respectively of TFT.
A second insulating film (protective insulating film)
30
is formed on the first insulating film (gate insulating film)
4
, covering the lamination structure from the amorphous silicon film
12
a
to the upper Ti film
17
a
. A contact hole
32
is formed through the protective insulating film
30
, in an area above the terminal
21
a
. A terminal protective conductive film
35
a
made of indium tin oxide (ITO) covers the inner surface of the contact hole
32
and the nearby surface of the protective insulating film
30
. The terminal protective conductive film
35
a
prevents corrosion and damages of the terminal
21
a
. The terminal protective conductive film
35
a
is formed at the same time when a pixel electrode is formed in the pixel area.
A probe is made in contact with the surface of the terminal protective conductive film
35
a
to conduct a conduction test and an insulation test. A terminal for a tape automatic bonding (TAB) terminal has a similar structure to that shown in FIG.
9
.
In the past, there was a case that when a probe was made in contact with the surface of the terminal protective conductive film
35
a
shown in
FIG. 9
, the probe broke through the terminal protective conductive film
35
a
and gave damages to the underlying upper Ti film
17
a
and Al film
16
a.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an ITO film contact structure capable of realizing good electrical contact between Al or Al alloy film and an ITO film, and improving productivity.
It is another object of the present invention to provide a TFT substrate and its manufacture method capable of realizing good electrical contact between Al or Al alloy film and an ITO film, and improving productivity.
It is another object of the present invention to provide a TFT substrate having a high connection reliability terminal structure hard to be damaged when a probe is made in contact with this structure.
According to one aspect of the present invention, there is provided an ITO film contact structure comprising: a conductive film made of Al or alloy containing Al as a main component; an upper conductive film disposed on said conductive film, formed with a first opening, and made of a material different from Al; an insulating film disposed on said upper conductive film and formed with a second opening, an inner wall of the second opening being retreated from an inner wall of the first opening; and an ITO film covering a partial upper surface of said insulating film and inner surfaces of the first and second openings, and contacting a partial upper surface of said upper conductive film at a region defining a part of the inner wall of the second opening.
Since the ITO film is connected via the upper conductive film to the conductive film, good electrical contact between the ITO film and conductive film can be established.
REFERENCES:
patent: 5998230 (1999-12-01), Gee-Sung et al.
patent: 6008065 (1999-12-01), Lee et al.
Fujikawa Tetsuya
Hayashi Shougo
Kihara Masahiro
Sukenori Hidetoshi
Tanaka Yoshinori
Fujitsu Limited
Greer Burns & Crain Ltd.
Tran Minh Loan
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