Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2008-06-24
2008-06-24
Pham, Hoai V (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257SE29117, C257SE29273
Reexamination Certificate
active
07391052
ABSTRACT:
A TFT is provided completely separated by an insulating film, in which a parasitic MOSFET is not generated at ends of a semiconductor layer, and the variation in characteristics is small. At least one portion of the ends in the gate-width direction of a gate electrode forming the TFT is disposed in a semiconductor region which forms the TFT, and the ends in the gate-length direction of the gate electrode extend toward the outside of the semiconductor region forming the TFT. With this arrangement, a uniform TFT in which a parasitic MOSFET is not generated at the ends in the gate-width direction is obtainable.
REFERENCES:
patent: 5316960 (1994-05-01), Watanabe et al.
patent: 5374564 (1994-12-01), Bruel
patent: 5412493 (1995-05-01), Kunii et al.
patent: 5517150 (1996-05-01), Okumura
patent: 5614730 (1997-03-01), Nakazawa et al.
patent: 5650636 (1997-07-01), Takemura et al.
patent: 5701167 (1997-12-01), Yamazaki
patent: 5703382 (1997-12-01), Hack et al.
patent: 5717473 (1998-02-01), Miyawaki
patent: 5729308 (1998-03-01), Yamazaki et al.
patent: 5748165 (1998-05-01), Kubota et al.
patent: 5777703 (1998-07-01), Nishikawa
patent: 6031589 (2000-02-01), Kim
patent: 6066860 (2000-05-01), Katayama et al.
patent: 6127235 (2000-10-01), Gardner et al.
patent: 6255705 (2001-07-01), Zhang et al.
patent: 6297518 (2001-10-01), Zhang
patent: 6306213 (2001-10-01), Yamazaki
patent: 6330044 (2001-12-01), Murade
patent: 6335778 (2002-01-01), Kubota et al.
patent: 6417896 (2002-07-01), Yamazaki et al.
patent: 6437367 (2002-08-01), Yamazaki et al.
patent: 6504215 (2003-01-01), Yamanaka et al.
patent: 6573955 (2003-06-01), Murade
patent: 6610997 (2003-08-01), Murade
patent: 6744198 (2004-06-01), Hirabayashi
patent: 6891588 (2005-05-01), Kawachi et al.
patent: 6909242 (2005-06-01), Kimura
patent: 6919886 (2005-07-01), Sato et al.
patent: 2002/0140643 (2002-10-01), Sato
patent: 2003/0011584 (2003-01-01), Azami et al.
patent: 2003/0094614 (2003-05-01), Yamazaki et al.
patent: A-4-346418 (1992-12-01), None
patent: A 05-088200 (1993-04-01), None
patent: 6163891 (1994-06-01), None
patent: A 07-066419 (1995-03-01), None
patent: A 07-092493 (1995-04-01), None
patent: A 08-116063 (1996-05-01), None
patent: A-9-246563 (1997-09-01), None
patent: A 10-301100 (1998-11-01), None
patent: WO 9816868 (1998-04-01), None
patent: WO99/35678 (1999-07-01), None
Oliff & Berridg,e PLC
Pham Hoai v
Seiko Epson Corporation
LandOfFree
TFT structure for suppressing parasitic MOSFET in active... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with TFT structure for suppressing parasitic MOSFET in active..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TFT structure for suppressing parasitic MOSFET in active... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2814243