Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2001-06-28
2003-12-09
Ton, Toan (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S046000, C349S187000
Reexamination Certificate
active
06661477
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of Korean Patent Application No. P2000-50429, filed on Aug. 29, 2000, the entirety of which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display and a method for fabricating the same, which has large aperture and can improve a poor picture quality caused by vertical cross talk.
2. Background of the Related Art
A related art liquid crystal display is provided with a liquid crystal panel, a light source, and a driving circuit. The liquid crystal panel has first and second substrates, and liquid crystal injected between the two substrates. The second substrate has a black matrix, a color filter layer, and a common electrode.
The first substrate has a plurality of gate lines running in one direction at fixed intervals, a plurality of data lines running in one direction perpendicular to the gate lines at fixed intervals, and an LCD array at crossing parts of the gate lines and the data lines.
In an LCD array region, a space region between the gate lines and data lines is a pixel region, in which a pixel electrode and a thin film transistor are provided. That is, the thin film transistor is provided with a gate electrode connected to the gate line, a source electrode connected to the data line, a data electrode connected to the pixel electrode, for being turned on selectively in response to a signal to the gate line to transfer a data signal from the data line to the pixel electrode. The gate lines and the data lines are electrically connected to driving circuits.
Vertical cross-talk in the liquid crystal display, caused by parasitic capacitance Cds between the source electrode and the drain electrode, degrades a picture quality as a source voltage (a data signal) to be provided to the pixels on a vertical (data) line influences the liquid crystal pixel voltage. The cross-talk mostly occurs as a static capacitance between the data line and the pixel electrode is increased. Research has been performed with a goal to reduce the vertical cross-talk in a liquid crystal display with a large aperture. In order to achieve the large aperture, an organic insulating film is used as a passivation film deposited between the data line and the pixel electrode, and the pixel electrode is overlapped with and edge of the data line.
A related art liquid crystal display and method for fabricating the same will be explained, with reference to the attached drawings.
FIG. 1
illustrates a layout of a first substrate of the related art liquid crystal display, and
FIG. 2
illustrates a section of the related art liquid crystal display across line I-I′ in
FIG. 1
, showing a pixel electrode, a data line, and a drain electrode.
Referring to
FIGS. 1 and 2
, the related art liquid crystal display is provided with an active layer
102
, a channel layer of a thin film transistor in an active region defined on an insulating substrate
101
, a gate insulating film (not shown) on the active layer
102
to surround the active layer
102
, and a gate electrode
103
a
crossing a central part of the active layer
102
on the gate insulating film. The gate electrode
103
a
is a projection from the gate line
103
running in one direction. There are source/drain regions in the active layer on both sides of the gate electrode
103
a
, an interlayer insulating film
104
on an entire surface inclusive of the gate electrode
103
a
, and first contact holes
106
to expose the source/drain regions in the active layer
102
by etching the interlayer insulating film
104
and the gate insulating film. The source electrode
105
a
, the drain electrode
105
b
, and the data line
105
are formed at each of the contact holes
106
and on the interlayer insulating film
104
. The data line
105
and the gate line
103
cross each other. An organic insulating film
107
is formed on the interlayer insulating film
104
inclusive of the source electrode
105
a
, the drain electrode
105
b
, and the dateline
105
. The organic insulating film
107
has a flat surface. There is a second contact hole
108
in the organic insulating film
107
to expose the drain electrode
105
b
, and a pixel electrode
109
of ITO (Indium Thin Oxide) in the second contact hole
108
and on the organic insulating film
107
. The pixel electrode
109
overlaps upper parts of edges of the data line
105
, except the central part thereof.
Referring to
FIG. 2
, in a large aperture structure, a distance ‘b’ between the pixel electrode
109
and the data line
105
is the most important element in view of the vertical crosstalk. That is, the greater the distance ‘b’, the smaller the parasitic capacitance between the pixel electrode
109
and the data line
105
, that improves the poor picture quality caused by the vertical crosstalk. However, the distance ‘b’ can not be made greater because an increased distance ‘b’ necessitates an increase of an etch depth ‘c’ of the second contact hole
108
provided for bringing the pixel electrode
109
into contact with the drain electrode
105
. In conclusion, ‘c’ is fixed depending on a dry etching (anisotropic etching) capability, ‘a’ is fixed depending on ‘c’, and ‘b’ is fixed depending on ‘c’. For an example, when ‘c’=9500 Å, ‘d’=3500 Å, ‘a’=1.3 &mgr;m, and ‘b’=0.95 &mgr;m. If ‘b’ is to be made thicker, then ‘c’ also has to be made thicker.
A method for fabricating the foregoing related art liquid crystal display will be explained. FIGS.
3
A~
3
C illustrate sections showing the steps of a method for fabricating the related art liquid crystal display.
Referring to
FIG. 3A
, an active layer
102
(see
FIG. 1
) is formed on an active region defined on an insulating substrate
101
, a gate insulating film (not shown) is formed on the active layer
102
to surround the active layer
102
, and a gate line
103
(see
FIG. 1
) is formed on the gate insulating film to run in one direction, together with a gate electrode
103
a
(see
FIG. 1
) projected from the gate line
103
to cross a central part of the active layer
102
. Source/drain regions are formed in the active layer on both sides of the gate electrode
103
a.
Then, as shown in
FIG. 3B
, an interlayer insulating film
104
is deposited on an entire surface inclusive of the gate electrode
103
a
, and the interlayer insulating film
104
and the gate insulating film are etched to expose the source/drain regions in the active layer
102
, to form a first contact hole
106
(see FIG.
1
). A metal layer is formed in respective first contact holes
106
to the source and drain regions and on the interlayer insulating film
104
, and subjected to anisotropic etching, to form a source electrode
105
a
(see
FIG. 1
) in contact with the source region, a drain electrode
105
b
in contact with the drain region, and a data line
105
extended from the source electrode to be in a perpendicular direction to the gate line
103
.
As shown in
FIG. 3C
, an organic insulating film
107
is coated on an entire surface of the source electrode
105
a
, the data line
105
, and the drain electrode
105
b
, and a second contact hole
108
is formed on the organic insulating film
107
to expose the drain electrode
105
b
. An ITO (Indium Tin Oxide) is deposited on an entire surface of the organic insulating film
107
inclusive of the second contact hole
108
, and subjected to anisotropic etching to expose a central part of the data line
105
, and overlaps upper part edges of the data line
105
, to form a pixel electrode
109
.
However, the foregoing related art liquid crystal display, and a method for fabricating the same, have the following problem.
The thicker organic insulating film formed between the data line and the pixel for reduction of a parasitic capacitance between the data line and the pixel electrode requires a longer time period in etching a sec
Ha Yong Min
Park Jae Deok
Yeo Ju Cheon
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