Liquid crystal cells – elements and systems – Particular excitation of liquid crystal – Electrical excitation of liquid crystal
Reexamination Certificate
2000-12-29
2002-06-04
Sikes, William L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular excitation of liquid crystal
Electrical excitation of liquid crystal
C349S042000, C349S138000, C349S187000, C349S192000, C349S054000, C257S048000, C345S092000
Reexamination Certificate
active
06400425
ABSTRACT:
The present application is based on Korean Patent Application No. 1999-26940, filed Jul. 5, 1999, the entirety of which is incorporated by reference in this application.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more, particularly, to an array substrate of an LCD device for testing the bus lines and a method of fabricating the same.
2. Discussion of the Related Art
In general, an LCD module has a display part and a non-display part or a pad part.
The display part of an LCD module usually has thin film transistors (TFTs) as switching devices. The display part of an LCD module is typically made up of two substrates having an interposed liquid crystal material. One substrate, referred to as the array substrate, includes a matrix array of TFTs and pixel electrodes. The array substrate also includes gate lines and source lines having gate electrodes and source electrodes, respectively. The opposing substrate, referred to as the color filter substrate, includes a light-shielding film (also known as a black matrix), a color filter, and a common electrode.
The pad part of an LCD module includes gate pads and source pads applying signal voltages and data voltages to the gate lines and the source lines, respectively. The gate pads are arranged on one side of the array substrate and the source pads are arranged on an adjacent side to the side having the gate pads.
Since the structure of the array substrate is complex, short/open-circuits can occur between the elements of the array substrate due to static electricity during a manufacturing process. In order to have the plural lines or elements of the array substrate in equipotential, shorting bars which are connected to every line formed. The shorting bars are removed in a cutting process after the array substrate is completed.
Referring to the attached drawings, an array substrate of an LCD device that is used for testing the short/open-circuit of the gate and source lines and that is manufactured by a conventional method will now be explained.
FIG. 1
is a partial plan view illustrating a pad part and inverse staggered type thin film transistors (TFTs) according to the conventional TFT array substrate. As shown in
FIG. 1
, the gate pad
15
is positioned on the left side of the substrate
10
and the source pad
39
is positioned on the upper side of the substrate
10
. A gate shorting bar
17
is arranged in a longitudinal direction at the left peripheral portion of the substrate
10
and a source shorting bar
18
is arranged in a transverse direction at the upper peripheral portion of the substrate
10
. A gate line
13
is arranged in a transverse direction on the substrate
10
and a source line
43
is arranged in a longitudinal direction on the substrate
10
. The gate and source lines
13
and
43
define the pixel region
58
. A TFT including a gate electrode
11
, an active layer
27
and source and drain electrodes
37
a
and
37
b
is positioned at one corner of the pixel region
58
and near the crossing point of the gate and source lines
13
and
43
. The other elements shown in
FIG. 1
will be explained with reference to
FIGS. 2A
to
2
F.
FIGS. 2A
to
2
F are cross-sectional views of line II—II of FIG.
1
and illustrate a manufacturing process of an array substrate according to the conventional art.
As shown in
FIG. 2A
, a first metallic or conductive material such as aluminum (Al) and Al-alloy is deposited on the substrate
10
. The material is patterned to form a gate line
13
, a gate electrode II extended from the gate line
13
, a gate pad
15
, a gate shorting bar
17
, a shorting bar connector
14
connecting the gate pad
15
with the gate shorting bar
17
, and a source shorting bar
18
and a source shorting bar connector
19
connecting a source pad
39
with the source shorting bar
18
. The source pad
39
is formed in a later step As a metal for the above-mentioned elements, aluminum is mainly used so as to reduce the RC delay from its low resistance. However, pure aluminum is weak in acidity and may result in line defects by a formation of a hillock during a high temperature process. Thus, an aluminum alloy may be used. In some cases, a double layered gate structure having another metal layer, such as chrome (Cr) or molybdenum (Mo) covering the aluminum or aluminum alloy layer, is used.
The gate shorting bar
17
is connected to the source shorting bar
18
so that the gate and source shorting bars
17
and
18
make a rectangular shape around the array substrate, i.e., they surround the pad part and the display part of the array substrate (see FIG.
1
). The gate shorting bar
17
is connected to every gate pad, which is connected to the gate lines, in order to maintain an equipotential state for the plural gate lines. Therefore, since the gate pad
15
and the gate line
13
have an equipotential by the gate shorting bar
17
, the open/short-circuit caused by static electricity during the manufacturing process is prevented.
Similar to the gate shorting bar connector
14
, the source shorting bar connector
19
connects the source shorting bar
17
and the source pad
39
(see
FIG. 1
) formed in a later process step.
Referring to
FIG. 2B
, the first insulation layer
21
including silicon nitride (SiN
x
) or silicon oxide (SiO
x
) is formed over the substrate and over the first metallic layer. At this time, the gate electrode II can be oxidized to form an aluminum oxide (Al
2
O
3
) layer on its surface using a mask process before depositing the insulation material. After forming the first insulation layer
21
, an intrinsic semiconductor layer
23
and a doped semiconductor layer
25
are sequentially formed on the first insulation layer
21
.
As shown in
FIG. 2C
, an active layer
27
and an ohmic contact layer
29
are formed in an island shape by patterning the intrinsic and doped semiconductor layers
23
and
25
at the same time. Then, a first gate pad contact hole
31
and a first source pad contact hole
33
are formed by patterning the first insulation layer
21
.
Referring to
FIG. 2D
, a second metallic or conductive material such as chrome or chrome alloy are deposited and patterned to form the source electrode
37
a,
the drain electrode
37
b,
the source line
43
connected to the source electrode
37
a,
a gate pad electrode
41
connected to the gate pad
15
via the first gate pad contact hole
31
, and the source pad
39
connected to the source shorting bar connector
19
via the first source pad contact hole
33
. Therefore, every source line is connected to the shorting bar
18
through the source shorting bar connector
19
, i.e., the source lines have equipotential. The portion of the ohmic contact layer
27
between the source electrode
37
a
and the drain electrode
37
b
is patterned to form spaced apart ohmic contact layers
35
a
and
35
b
using the gate and source electrodes
37
a
and
37
b
as masks.
As shown in
FIG. 2E
, a second insulation layer
45
is formed on the entire resultant surface and patterned to form a second gate pad contact hole
47
, a gate cutting hole
53
penetrating the first and second insulation layers
21
and
45
. A second source pad contact hole
51
and a drain contact hole
49
are also formed in this patterning process. Then, the portion of the gate shorting bar connector
14
, which is exposed by the gate cutting hole
53
, is etched (see “B” of FIG.
1
).
The reason for forming the gate cutting hole
53
is that the gate lines neighboring each other are examined for possible shorts or opens. For the purpose of these tests, the gate lines are generally classified into even-numbered and odd-numbered gate lines, and electric signals are applied. If the even-numbered gate pads connected to the even-numbered gate lines contact the right side shorting bar (not shown), the odd-numbered gate pads connected to the odd-numbered gate lines contact the left side shorting bar
17
. If the electric signals are applied to the left-side shorting bar, a line
Kim Ki-Tae
Lee Seong-Su
Chowdhury Tarifur R.
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
Sikes William L.
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