Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-01-09
2007-01-09
Shankar, Vijay (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S088000, C345S090000, C345S093000, C345S099000
Reexamination Certificate
active
10789457
ABSTRACT:
A programmable controller having three well-known components used in display controls but put under the control of a programmable ‘sub-field ’ timing generator is disclosed. The three well-known components include a Phase Lock Loop (PLL) unit, a Pixel Pipe Line (PPL) unit and an embedded frame buffer. Even though these are well known and understood components, each one is implemented to support the field and sub-field concepts of field sequential color (FSC) as well as non-FSC TFT display devices. The programmable controller also includes some new components that are unique to FSC displays. These new components include a color light sequencer to control the LED controls (or whatever color light source used) and programmable Source and Gate driver controls to accommodate the extremely wide diversification between different display panels.
REFERENCES:
patent: 6624813 (2003-09-01), Wang
patent: 2002/0149598 (2002-10-01), Greier et al.
Nally Robert M.
Okita Masaya
Flynn ,Thiel, Boutell & Tanis, P.C.
Hunet Display Technology Inc.
Shankar Vijay
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