Textured semiconductor wafer for solar cell

Details Textured semiconductor wafer for solar cell Textured semiconductor wafer for solar cell

2001-11-26

2003-12-16

Loney, Donald J. (Department: 1772)

Stock material or miscellaneous articles

Structurally defined web or sheet

Including variation in thickness

C428S167000, C216S099000, C136S256000

Reexamination Certificate

active

06663944

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for METHOD OF TEXTURING SEMICONDUCTOR SUBSTRATE FOR SOLAR CELL earlier filed in the Korean Industrial Property Office on Jan. 3, 2001 and there duly assigned Serial No. 2001-251.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solar cell and more particularly a textured semiconductor wafer for a solar cell.
2. Description of the Related Art
A solar cell includes a junction of a p-type semiconductor and an n-type semiconductor (pn junction). In the cell, electron-hole pairs are generated by photon. The generated electrons and holes respectively move toward the p-type and n-type semiconductors, and then accumulated in two contacts. When light shining on the solar cell produces both a current and a voltage, the light-generated current and voltage can be used as electric power.
A performance of such a solar cell depends on the conversion efficiency from light energy into electric energy. The conversion efficiency is represented as a ratio of electric output of the solar cell to an amount of incident light.
Accordingly, a variety of solar cells have been developed to improve the conversion efficiency. As an example, a method for maximizing the light absorption by texturing the surface of a solar cell wafer has been proposed. To texture the surface of the wafer, various methods such as chemical etching, plasma etching, mechanical scribing, and photolithography have been used.
Particularly, the chemical etching is widely used as it has an advantage that a lot of wafers can be quickly textured with less expenses. An isotropic etching and anisotropic etching are well known as the chemical etching.
U.S. Pat. No. 5,949,123 issued to Le et al. for Solar Cell Including Multi-crystalline Silicon and a Method of Texturizing the Surface of P-type Multi-crystalline Silicon, discloses such isotropic etching for texturing polycrystalline silicon wafer using oxidizing solution having fluorine ions.
FIG. 4
is a schematic view of the polycrystalline silicon wafer surface
10
textured according to this method and illustrates a path of the incident light
20
to the textured surface
10
. However, a polycrystalline silicon wafer surface textured according to this method is designed to deteriorate the light absorption efficiency as light cannot bound more than two times at the textured surface.
U.S. Pat. No. 5,804,090 issued to Iwasaki et al for Process for Etching Semiconductors Using a Hydrazine and Metal Hydroxide-containing Etching Solution discloses such anisotropic etching, in which hydrazine hydrate functioning as a protector and metal hydroxide solution as etching solution are used. This anisotropic etching is very effective for a single crystalline silicon wafer, but has an identical problem to the isotropic etching for a polycrystalline silicon wafer.
In addition, the mechanical scribing, plasma etching, and photolithography are all time consuming and costly.
Therefore, there is a need for chemical etching that can effectively texture the surface of the polycrystalline silicon wafer.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a textured polycrystalline silicon wafer and a single crystalline silicon wafer with less expense, while improved light absorption efficiency.
To achieve the above and other objectives, the present invention provides a textured semiconductor wafer for a solar cell. The textured semiconductor wafer includes a plurality of grooves being formed on a surface of the semiconductor wafer. The grooves are formed in the step of depositing a protector on the surface randomly by spray process or screen-printing process, dipping the wafer into an isotropic etching solution to etch a portion of the surface where the protector is not deposited, and removing the protector. Particularly, when using the spray process, the protector is deposited on a surface of the wafer at the random distribution.
A shape of the groove is concaved to make the incident light bound the surface more than one time.
The semiconductor wafer is silicon wafer.
The protector is deposited on more than 90% of an entire area of the surface.
The protector is formed of organic or inorganic material that does not reacts with etching solution but can be easily deposited and removed, and endure an annealing process. Preferably, the protector is formed of a material selected from the group including photoresist, silicon oxide, TiO
2
, and NaNO
2
.
The isotropic etching solution is an acid-based solution. Preferable, the isotropic etching solution is selected from the group including HF, HNO
3
, a mixture of HF and HNO
3
, phosphoric acid, acetic acid, a mixture of phosphoric acid and water, and a mixture of acetic acid and water.


REFERENCES:
patent: 4916503 (1990-04-01), Uematsu et al.
patent: 5258077 (1993-11-01), Shahryar et al.
patent: 5804090 (1998-09-01), Iwasaki et al.
patent: 5949123 (1999-09-01), Le et al.
patent: 5997990 (1999-12-01), Kambara et al.

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