Testing VLSI circuits for defects

Details Testing VLSI circuits for defects Testing VLSI circuits for defects

1994-03-17

1996-04-09

Ramirez, Ellis B.

Excavating

364489, 364490, 371 222, G01R 31317

Patent

active

055068529

ABSTRACT:
A method based on continuous optimization techniques for generating test vectors for use in testing VLSI circuits includes representing digital circuits as smooth functions. The test generation problem is formulated as the minimization of the objective function over a hypercube in Euclidean space. The dimension of the space is equal to the number of primary inputs of the circuit. The smooth function is optimized inside a convex polytope using a variant of gradient descent and line search strategies. The solution starts at the center of the hypercube and follows a trajectory to one of the corners of the hypercube that corresponds to a test vector. Once the test vector is determined by this method, electrical signals corresponding to the test vector are applied to the inputs of the VLSI circuits. The outputs of the VLSI circuit are monitored in order to locate defects in the circuit. The representation of the logic gates as a continuous family of functions enables the method to quickly find an optimal solution to the test generation problem.

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patent: 5001418 (1991-03-01), Posse et al.
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S. T. Chakradhar et al, "Test Generation Using Neural Computers", International Journal of Computer Aided VLSI Design, vol. 3, Mar. 1991, pp. 241-257.
Kazumi Hatayama et al, "Sequential Test Generation Based on Real-Valued Logic Simulation", Proceedings of the International Test Conference 1992, pp. 41-48.
Kwang-Ting Cheng et al "Unified Methods for VLSI Simulation and Test Generation," by Kluwer Academic Publishers, 1989, Chapter 6, pp. 67-86.

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