Testing unit and self-evaluating device

Details Testing unit and self-evaluating device Testing unit and self-evaluating device

1999-08-27

2003-07-08

Bui, Bryan (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

C702S118000, C702S119000, C702S120000, C714S100000

Reexamination Certificate

active

06591211

ABSTRACT:

FIELD
The present invention relates to the testing of devices. More particularly, the present invention relates to the testing of a self-evaluating device.
BACKGROUND
When a device is manufactured, testing may be performed to verify that the device operates properly. For example, a logic device, such as a processor used in a personal computer, may be tested to verify that the logic device properly performs various functions.
FIG. 1
is a block diagram illustrating a known testing unit
100
and a device being tested
150
. The testing unit
100
includes a storage unit
110
, such as a memory, that stores test data. The test data is sent to the device being tested
150
through a communication port
120
. If the device being tested is a processor, the communication port
120
may have a large number of channels, such as several hundred channels, that stimulate the processor by sending test data to the processor's input pins. A large number of sets of test data, such as several million test “vectors,” may be sent at a high frequency to thoroughly test the processor's operation.
The device being tested
150
receives the test data and produces test result data. For example, a processor may receive instructions through input pins and generate results that are available through the processor's output pins. The test result data is received by the testing unit
100
through another communication port
130
, which may also contain a large number of channels. The testing unit
100
can sample, or “strobe,” these channels to capture the test result data.
The testing unit
100
includes a comparing unit
140
that compares the test result data with expected test result data stored in the storage unit
110
. Based on the comparison, test status data, such as a “pass” or “fail” indication, is generated by the testing unit
100
. For example, a processor may be expected to generate a certain result when provided with a known set of instructions. By comparing the actual result with the expected result, the testing unit
100
can evaluate if the device being tested
150
is functioning properly.
The use of such a testing unit
100
, however, has several disadvantages. Unless the number of channels used in the communication port
130
is increased, only a single device
150
can be tested at a given time. For example, if each device being tested has 300 output channels, the communication port
130
would need 900 channels to simultaneously test three devices. That is, the testing unit would receive three sets of test result data, each using 300 channels. Moreover, the testing unit
100
may need additional comparing units to evaluate the test result data from the three devices. These changes would increase the cost of the testing unit
100
.
As a result, known testing units
100
evaluate devices one at a time, in series, which increases production testing throughput time and ultimately increases the cost of the device. If multiple devices must be tested in parallel, separate testing units, which can cost millions of dollars each, are required. In addition, using additional testing units may require additional floor space and maintenance, which also increase the cost of the device.
It is also known that a device can incorporate a limited “self-test” or “built-in-test” function. These tests, however, do not use external test data and/or expected test result data, and the coverage of such tests are relatively low. For example, a built-in-test may not be able to generate the millions of test vectors required to completely test the device. In addition, even a limited built-in-test can make the design of the device extremely complex. Moreover, because the built-in-test is designed within a device, it cannot be easily modified.
SUMMARY
In accordance with one embodiment of the present invention, an apparatus for testing a device comprises a test data communication port adapted to output test data to the device. The apparatus also comprises an expected test result data communication port adapted to output expected test result data to the device.
In accordance with another embodiment of the present invention, an apparatus comprises a test data communication port adapted to receive test data from a testing unit. The apparatus also comprises an expected test result data communication port adapted to receive expected test result data from the testing unit.


REFERENCES:
patent: 5696772 (1997-12-01), Lesmeister
patent: 5875293 (1999-02-01), Bell et al.
patent: 6028439 (2000-02-01), Arkin et al.
patent: 6066822 (2000-05-01), Nemoto et al.

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