Testing system for semiconductor device

Details Testing system for semiconductor device Testing system for semiconductor device

2000-04-13

2002-10-01

Le, N. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C714S724000

Reexamination Certificate

active

06459292

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a testing system for a semiconductor device to test the semiconductor device, more specifically relates to the testing system for the semiconductor device capable of a high-speed judgment concerning repair of a semiconductor memory.
In a step of manufacturing the semiconductor memory so far, memory repair steps as follows is necessary: a function test is carried out for semiconductor memory devices in a status of a wafer before packaging and a defect cell is detected on the basis of fail information as a result of the test to replace to a spare cell. There is one of testing systems for semiconductor devices, having hardware named memory repair analyzer of exclusive use for yielding a repairable resolution to replace a defect cell detected to a spare cell.
FIG. 4
is a view showing an outlined configuration of the conventional testing system for semiconductor devices, having the memory repair analyzer. The testing system for semiconductor devices comprises a work station
1
(EWS), a tester processor (TP)
2
, a tester (TESTER)
3
, and a memory repair analyzer (MRA)
5
. The work station
1
works as an environment processor, mediates the instruction of a work and the notification of a result between a user and the tester, and controls whole of the testing system for semiconductor devices. More specifically, the work station
1
loads a test program on the tester processor
2
to operate a function test and starts up a repair analytical process according to a request outputted from the tester processor
2
to execute a repair analysis by the memory repair analyzer
5
. The tester processor
2
works an interface between the work station
1
and the tester
3
and executes a test program, which has been compiled by the work station
1
by loading, on a internal memory, and carries out processing of device measurement such as various tests of functions and a parametric test of DC. The tester
3
comprises an algorithmic pattern generator (ALPG), programmable data selector (PDS), a timing generator, a failure analysis memory
4
, a format control, a digital compare, and a DC parametric test unit, which are connected each other via a tester bus used for data transfer. In
FIG. 4
, only the failure analysis memory
4
is shown and other units have been omitted inconvenience of explanation. In the failure analysis memory
4
, a fail data, as a result of the function test, is stored. The memory repair analyzer
5
operates the following series of the processes of the repair analysis: taking the fail data stored in the failure analysis memory
4
into a fail buffer memory, synchronizing to an analysis start signal outputted from the work station
1
, detecting a failure cell on the basis of the fail data thereof, finding out a necessary repair resolution in order to make the semiconductor device to a product without defect by replacing the failure cell to a spare cell, and sending the repair resolution to the work station
1
.
The above described testing system for semiconductor devices can execute a device measurement (function test) by the tester
3
and a repair analysis by the memory repair analyzer
5
in parallel. Before operating the repair analysis, it is necessary to execute device measurement (function test) by the tester
3
and to previously store the fail data as the result in the failure analysis memory
4
. Therefore, in the conventional testing system for semiconductor devices, the tester processor
2
instructs to transfer the fail data from the failure analysis memory
4
to the fail buffer memory of the memory repair analyzer
5
and also instructs to operate the repair analytical process to the work station
1
in the point of the end of the first function test.
The work station
1
received the instruction to execute the repair analysis reads the repair analytical process from a hard disk to start up, reads a file necessary for the analyzing from the hard disk to prepare an analysis data, and sends the analysis data to the memory repair analyzer
5
. The memory repair analyzer
5
received the analysis data operates the repair analysis on the basis of the fail data stored in the fail buffer memory, and prepare a repair solution data to return to the work station
1
.
The work station
1
received the repair solution data records the repair solution data on the hard disk and notifies finish of the repair analysis to the tester processor
2
. The tester
3
has been operating in parallel the next second function test already during the repair analysis by the work station
1
and the memory repair analyzer
5
. Therefore, the tester processor
2
received the signal of finish of the repair analysis instructs operation of the repair analysis corresponding to the second function test to the work station
1
and the memory repair analyzer
5
as same as the above described steps, in the point of finish of the second function test. When the second function test had been finished before finish of the repair analysis, the tester processor
2
instructs operation of the repair analysis corresponding to the second function test in the point of receiving the notice of finish of the repair analysis.
Through such steps, by a parallel execution of the repair analysis and the function tests allows the repair analysis and the function test efficiently and in a high speed. Thus, very high throughput is achieved as a whole of the system. However, for test of the semiconductor device, a test may be carried out by reflecting the result of the repair analysis, which corresponds to the first function test previously carried out, to the next function test. For example, as a result of the repair analysis, the total number of testing hours can be shortened for a device determined as unrepairable (NO-GO (defect product)) by omitting the next second function test and the repair analysis corresponding thereto. In such a case, the next second function test should be operated by waiting completion of the repair analysis. This points out the following problems: the function test and the repair analysis should be operated in serial order and alternately; throughput cannot be improved by parallel processing. Also it is a problem that drop of throughput prolongs the time necessary for the repair analysis.
SUMMARY OF THE INVENTION
The present invention has created in consideration of these problems. An object of the invention is to provide a testing system for a semiconductor device allowing parallel operation of the function test and the repair analysis by reflecting the result of the repair analysis to the next test.
Another object of the present invention is to provide a testing system for a semiconductor device allowing shortening of a whole testing time for the repair analysis.
The testing system of the present invention for a semiconductor device, configured by tester unit carrying out a given test for a semiconductor device, host computer unit carrying out a repair analysis processing on the basis of a test result of the tester unit, tester controlling unit instructing the tester unit to operate the test by controlling the tester unit and notify the host computer unit to operate the repair analysis processing on the basis of the test result, wherein the host computer unit sends those data to the tester controlling unit in the point in which data showing repairable or unrepairable is detected as a result of the repair analysis processing to carry out processing for seeking a repair solution for those repairable.
It is important whether the semiconductor device is repairable or unrepairable in case of carrying out a test by reflecting the result of a repair analysis corresponding to previous first function test to the next function test in a test of the semiconductor device. The repair solution itself is not reflected to the next function test. Therefore, in the present invention, the next second function test and the repair analysis processing corresponding thereto can be omitted on the basis of data showing unrepairable status to m

Affiliated with

Also associated with

Rating

Testing system for semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing system for semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing system for semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2920536